Fix pin_layout contains bug

compiler/base/pin_layout.py

@@ -122,14 +122,20 @@ class pin_layout:
 
         (ll,ur) = self.rect
         (oll,our) = other.rect
-
-
+        
+        # Check if the oll is inside the y range
         if not (oll.y >= ll.y and oll.y <= ur.y):
             return False
-
+        # Check if the oll is inside the x range
         if not (oll.x >= ll.x and oll.x <= ur.x):
             return False
-
+        # Check if the our is inside the y range
+        if not (our.y >= ll.y and our.y <= ur.y):
+            return False
+        # Check if the our is inside the x range
+        if not (our.x >= ll.x and our.x <= ur.x):
+            return False
+        
         return True
         
     

compiler/router/pin_group.py

@@ -36,7 +36,7 @@ class pin_group:
         """
         local_debug = False
         if local_debug:
-            debug.info(0,"INITIAL:",pin_list)
+            debug.info(0,"INITIAL: {}".format(pin_list))
         
         # Make a copy of the list to start
         new_pin_list = pin_list.copy()
@@ -48,12 +48,14 @@ class pin_group:
                 if pin1 == pin2:
                     continue
                 if pin2.contains(pin1):
+                    if local_debug:
+                        debug.info(0,"{0} contains {1}".format(pin1,pin2))
                     # It may have already been removed by being enclosed in another pin
                     if pin1 in new_pin_list:
                         new_pin_list.remove(pin1)
                         
         if local_debug:
-            debug.info(0,"FINAL  :",new_pin_list)
+            debug.info(0,"FINAL  : {}".format(new_pin_list))
         return new_pin_list
 
     # FIXME: This relies on some technology parameters from router which is not clean.
@@ -68,9 +70,6 @@ class pin_group:
             enclosure = self.router.compute_pin_enclosure(ll, ur, ll.z)
             pin_list.append(enclosure)
 
-        print("ENCLOS",pin_list)
-        #return pin_list
-        # We used to do this, but smaller enclosures can be
         return self.remove_redundant_shapes(pin_list)
         
     def compute_enclosure(self, pin, enclosure):

compiler/router/supply_router.py

@@ -71,7 +71,7 @@ class supply_router(router):
 
         # Get the pin shapes
         self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
-        self.write_debug_gds("pin_enclosures.gds",stop_program=True)
+        #self.write_debug_gds("pin_enclosures.gds",stop_program=True)
 
         # Add the supply rails in a mesh network and connect H/V with vias
         # Block everything