mirror of https://github.com/VLSIDA/OpenRAM.git
Unrotate vias in delay chain
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5a065cf701
commit
93a6247f26
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@ -186,7 +186,7 @@ class delay_chain(design.design):
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continue
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for pin_name in ["vdd", "gnd"]:
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pin = load.get_pin(pin_name)
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self.add_power_pin(pin_name, pin.rc(),rotate=0)
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self.add_power_pin(pin_name, pin.rc())
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else:
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# We have an even number of rows, so need to get the last gnd rail
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inv = self.driver_inst_list[-1]
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@ -195,7 +195,7 @@ class delay_chain(design.design):
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continue
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pin_name = "gnd"
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pin = load.get_pin(pin_name)
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self.add_power_pin(pin_name, pin.rc(),rotate=0)
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self.add_power_pin(pin_name, pin.rc())
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# input is A pin of first inverter
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