mirror of https://github.com/VLSIDA/OpenRAM.git
Create VCG using nets as nodes rather than pins.
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@ -602,6 +602,7 @@ class layout(lef.lef):
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"""
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Connect a mapping of pin -> name for a bus. This could be
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replaced with a channel router in the future.
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NOTE: This has only really been tested with point-to-point connections (not multiple pins on a net).
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"""
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(horizontal_layer, via_layer, vertical_layer)=layer_stack
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if horizontal:
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@ -720,6 +721,7 @@ class layout(lef.lef):
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try to minimize the number of tracks -- instead, it picks an order to avoid the vertical
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conflicts between pins.
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"""
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local_debug = True
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def remove_net_from_graph(pin, g):
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# Remove the pin from the keys
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@ -732,6 +734,29 @@ class layout(lef.lef):
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g[other_pin]=conflicts
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return g
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def vcg_pins_overlap(pins1, pins2, vertical):
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# Check all the pin pairs on two nets and return a pin
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# overlap if any pin overlaps vertically
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for pin1 in pins1:
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for pin2 in pins2:
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if vcg_pin_overlap(pin1, pin2, vertical):
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return True
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return False
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def vcg_pin_overlap(pin1, pin2, vertical):
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# Check for vertical overlap of the two pins
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# Pin 1 must be in the "LEFT" set and overlap the right
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x_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().x-pin2.center().x)<pitch
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# Pin 1 must be in the "TOP" set and overlap the bottom
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y_overlap = pin1.by() > pin2.by() and abs(pin1.center().y-pin2.center().y)<pitch
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return (not vertical and x_overlap) or (vertical and y_overlap)
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if not pitch:
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pitch = self.m2_pitch
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@ -744,22 +769,38 @@ class layout(lef.lef):
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# Initialize the vertical conflict graph (vcg) and make a list of all pins
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vcg = {}
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# Create names for the nets for the graphs
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nets = {}
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index = 0
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print(route_map)
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for pin_connections in route_map:
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net_name = "n{}".format(index)
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print("N",net_name)
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index += 1
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nets[net_name] = []
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for pin_name in pin_connections:
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pin = all_pins[pin_name]
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nets[net_name].append(pin)
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if local_debug:
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import pprint
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pprint.pprint(nets)
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# Find the vertical pin conflicts
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# FIXME: O(n^2) but who cares for now
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for top_name,top_pin in top_pins.items():
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vcg[top_name]=[]
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for bot_name,bot_pin in bottom_pins.items():
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# Remember, vertical is the boolean of the routes in the channel
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# so check the intervals of the pins in the other dimension
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x_overlap = abs(top_pin.center().x-bot_pin.center().x)<pitch
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y_overlap = abs(top_pin.center().y-bot_pin.center().y)<pitch
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if (vertical and y_overlap) or (not vertical and x_overlap):
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for net_name1 in nets:
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print("NET1:",net_name1)
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vcg[net_name1]=[]
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for net_name2 in nets:
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print("NET2:",net_name2)
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# Skip yourself
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if net_name1 == net_name2:
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continue
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if vcg_pins_overlap(nets[net_name1], nets[net_name2], vertical):
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try:
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vcg[bot_name].append(top_name)
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vcg[net_name1].append(net_name2)
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except:
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vcg[bot_name] = [top_name]
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vcg[net_name1] = [net_name2]
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#FIXME: What if we have a cycle?
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@ -773,27 +814,28 @@ class layout(lef.lef):
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# list of routes to do
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while vcg:
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#print(vcg)
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if local_debug:
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from pprint import pformat
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print("VCG:\n",pformat(vcg))
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# get a route from conflict graph with empty fanout set
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route_pin=None
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for route_pin,conflicts in vcg.items():
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net_name=None
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for net_name,conflicts in vcg.items():
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if len(conflicts)==0:
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vcg=remove_net_from_graph(route_pin,vcg)
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vcg=remove_net_from_graph(net_name,vcg)
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break
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else:
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# FIXME: We don't support cyclic VCGs right now.
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debug.error("Cyclic VCG in channel router.",-1)
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if local_debug:
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print("Routing:",net_name,pin_connections)
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# Get the connected pins from the routing map
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for pin_connections in route_map:
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if route_pin in pin_connections:
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break
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#print("Routing:",route_pin,pin_connections)
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# These are the pins we'll have to connect
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pin_list = nets[net_name]
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# Remove the net from other constriants in the VCG
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vcg=remove_net_from_graph(net_name, vcg)
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# Remove the other pins from the conflict graph too
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for other_pin in pin_connections:
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vcg=remove_net_from_graph(other_pin, vcg)
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# Create a list of the pins rather than a list of the names
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pin_list = [all_pins[pin_name] for pin_name in pin_connections]
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# Add the trunk route and move up to next track
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if vertical:
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self.add_vertical_trunk_route(pin_list, offset, layer_stack, pitch)
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@ -23,8 +23,8 @@ class sram_1bank_test(openram_test):
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c.words_per_row=1
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debug.info(1, "Single bank, no column mux with control logic")
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a = sram(c, "sram1")
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self.local_check(a, final_verification=True)
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#a = sram(c, "sram1")
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#self.local_check(a, final_verification=True)
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c.num_words=32
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c.words_per_row=2
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