mirror of https://github.com/VLSIDA/OpenRAM.git
Fix wrong exception handling that depended on order. Replaced with if/else instead.
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@ -754,36 +754,42 @@ class layout(lef.lef):
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"""
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def remove_net_from_graph(pin, g):
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# Remove the pin from the keys
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"""
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Remove the pin from the graph and all conflicts
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"""
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g.pop(pin,None)
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# Remove the pin from all conflicts
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# This is O(n^2), so maybe optimize it.
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# FIXME: This is O(n^2), so maybe optimize it.
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for other_pin,conflicts in g.items():
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if pin in conflicts:
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conflicts.remove(pin)
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g[other_pin]=conflicts
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return g
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def vcg_pins_overlap(pins1, pins2, vertical):
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# Check all the pin pairs on two nets and return a pin
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# overlap if any pin overlaps vertically
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for pin1 in pins1:
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for pin2 in pins2:
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def vcg_nets_overlap(net1, net2, vertical):
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"""
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Check all the pin pairs on two nets and return a pin
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overlap if any pin overlaps
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"""
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for pin1 in net1:
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for pin2 in net2:
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if vcg_pin_overlap(pin1, pin2, vertical):
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return True
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return False
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def vcg_pin_overlap(pin1, pin2, vertical):
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# Check for vertical overlap of the two pins
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""" Check for vertical or horizontal overlap of the two pins """
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# Pin 1 must be in the "TOP" set
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x_overlap = pin1.by() > pin2.by() and abs(pin1.center().x-pin2.center().x)<pitch
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# Pin 1 must be in the "LET" set
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# Pin 1 must be in the "LEFT" set
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y_overlap = pin1.lx() < pin2.lx() and abs(pin1.center().y-pin2.center().y)<pitch
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return (not vertical and x_overlap) or (vertical and y_overlap)
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overlaps = (not vertical and x_overlap) or (vertical and y_overlap)
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return overlaps
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@ -813,16 +819,16 @@ class layout(lef.lef):
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# Find the vertical pin conflicts
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# FIXME: O(n^2) but who cares for now
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for net_name1 in nets:
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vcg[net_name1]=[]
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if net_name1 not in vcg.keys():
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vcg[net_name1]=[]
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for net_name2 in nets:
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if net_name2 not in vcg.keys():
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vcg[net_name2]=[]
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# Skip yourself
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if net_name1 == net_name2:
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continue
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if vcg_pins_overlap(nets[net_name1], nets[net_name2], vertical):
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try:
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vcg[net_name2].append(net_name1)
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except:
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vcg[net_name2] = [net_name1]
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if vcg_nets_overlap(nets[net_name1], nets[net_name2], vertical):
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vcg[net_name2].append(net_name1)
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#FIXME: What if we have a cycle?
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