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OpenRAM
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Merge branch 'dev' into supply_routing

This commit is contained in:
Matt Guthaus 2018-10-17 09:47:18 -07:00
parent 5cb3a24b19 5d6944953b
commit 4bf1e206e2
13 changed files with 409 additions and 821 deletions
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1
compiler/base/design.py
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@ -43,6 +43,7 @@ class design(hierarchy_design):
self.poly_to_active = drc("poly_to_active")
self.poly_extend_active = drc("poly_extend_active")
self.poly_to_polycontact = drc("poly_to_polycontact")
self.contact_to_gate = drc("contact_to_gate")
self.well_enclose_active = drc("well_enclosure_active")
self.implant_enclose_active = drc("implant_enclosure_active")

1075
compiler/bitcells/pbitcell.py
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File diff suppressed because it is too large Load Diff

2
compiler/characterizer/lib.py
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@ -544,7 +544,7 @@ class lib:
self.corner[1],
self.corner[2],
self.corner[0],
round_time(self.char_results["min_period"]),
round_time(self.char_sram_results["min_period"]),
self.out_dir,
lib_name))

1
compiler/example_config_scn4m_subm.py
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@ -9,4 +9,3 @@ temperatures = [ 25 ]
output_path = "temp"
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)

2
compiler/modules/control_logic.py
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@ -95,7 +95,7 @@ class control_logic(design.design):
# FIXME: These should be tuned according to the size!
delay_stages = 4 # Must be non-inverting
delay_fanout = 3 # This can be anything >=2
bitcell_loads = int(math.ceil(self.num_rows / 5.0))
bitcell_loads = int(math.ceil(self.num_rows / 2.0))
self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_"+self.port_type)
self.add_mod(self.replica_bitline)

9
compiler/pgates/precharge.py
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@ -78,13 +78,14 @@ class precharge(pgate.pgate):
self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
# Add the M1->M2->M3 stack at the left edge
vdd_contact_pos = vector(0.5*self.width, vdd_position.y + 0.5*self.m1_width)
self.add_via_center(layers=("metal1", "via1", "metal2"),
offset=vdd_pos.scale(0,1))
offset=vdd_contact_pos)
self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=vdd_pos.scale(0,1))
offset=vdd_contact_pos)
self.add_layout_pin_rect_center(text="vdd",
layer="metal3",
offset=vdd_pos.scale(0,1))
offset=vdd_contact_pos)
def create_ptx(self):
@ -112,7 +113,7 @@ class precharge(pgate.pgate):
# adds the lower pmos to layout
#base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
self.lower_pmos_position = vector(self.bitcell.get_pin(self.bitcell_bl).lx(),
self.lower_pmos_position = vector(max(self.bitcell.get_pin(self.bitcell_bl).lx(), self.well_enclose_active),
self.pmos.active_offset.y)
self.lower_pmos_inst.place(self.lower_pmos_position)

64
compiler/tests/22_ngspice_psram_func_test.py
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@ -1,64 +0,0 @@
#!/usr/bin/env python3
"""
Run a regression test on various srams
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 22_psram_func_test")
class psram_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.bitcell = "pbitcell"
OPTS.replica_bitcell="replica_pbitcell"
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=2
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 1
OPTS.num_r_ports = 1
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank. Multiport with {}RW {}W {}R.".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports))
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f.num_cycles = 5
(fail,error) = f.run()
self.assertTrue(fail,error)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

56
compiler/tests/22_ngspice_sram_func_test.py
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@ -1,56 +0,0 @@
#!/usr/bin/env python3
"""
Run a regression test on various srams
"""
import unittest
from testutils import header,openram_test
import sys,os
sys.path.append(os.path.join(sys.path[0],".."))
import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 22_sram_func_test")
class sram_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=2
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank")
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
f = functional(s.s, tempspice, corner)
f.num_cycles = 10
(fail, error) = f.run()
self.assertTrue(fail,error)
globals.end_openram()
# instantiate a copdsay of the class to actually run the test
if __name__ == "__main__":
(OPTS, args) = globals.parse_args()
del sys.argv[1:]
header(__file__, OPTS.tech_name)
unittest.main()

4
compiler/tests/22_hspice_psram_func_test.py → compiler/tests/22_psram_func_test.py
View File

@ -16,7 +16,7 @@ class psram_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="hspice"
#OPTS.spice_name="hspice"
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.bitcell = "pbitcell"
@ -33,7 +33,7 @@ class psram_func_test(openram_test):
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_words=64,
num_banks=1)
c.words_per_row=2

4
compiler/tests/22_hspice_sram_func_test.py → compiler/tests/22_sram_func_test.py
View File

@ -16,7 +16,7 @@ class sram_func_test(openram_test):
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="hspice"
#OPTS.spice_name="hspice"
OPTS.analytical_delay = False
# This is a hack to reload the characterizer __init__ with the spice version
@ -30,7 +30,7 @@ class sram_func_test(openram_test):
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_words=64,
num_banks=1)
c.words_per_row=2
debug.info(1, "Functional test for 1bit, 16word SRAM, with 1 bank")

4
technology/freepdk45/tech/tech.py
View File

@ -66,6 +66,10 @@ parameter={}
parameter["min_tx_size"] = 0.09
parameter["beta"] = 3
parameter["6T_inv_nmos_size"] = 0.205
parameter["6T_inv_pmos_size"] = 0.09
parameter["6T_access_size"] = 0.135
drclvs_home=os.environ.get("DRCLVS_HOME")
drc = design_rules("freepdk45")

4
technology/scn3me_subm/tech/tech.py
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@ -52,6 +52,10 @@ parameter={}
parameter["min_tx_size"] = 4*_lambda_
parameter["beta"] = 2
parameter["6T_inv_nmos_size"] = 8*_lambda_
parameter["6T_inv_pmos_size"] = 3*_lambda_
parameter["6T_access_size"] = 4*_lambda_
drclvs_home=os.environ.get("DRCLVS_HOME")
drc = design_rules("scn3me_subm")

4
technology/scn4m_subm/tech/tech.py
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@ -54,6 +54,10 @@ parameter={}
parameter["min_tx_size"] = 4*_lambda_
parameter["beta"] = 2
parameter["6T_inv_nmos_size"] = 8*_lambda_
parameter["6T_inv_pmos_size"] = 3*_lambda_
parameter["6T_access_size"] = 4*_lambda_
drclvs_home=os.environ.get("DRCLVS_HOME")
drc = design_rules("scn4me_sub")