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Jesse Cirimelli-Low 2018-10-11 16:04:43 -07:00
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compiler/datasheet/datasheets/sram_2_16_1_scn4m_subm.html
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<style>
#data {
font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;
border-collapse: collapse;
width: 100%;
max-width: 800px
}
#data td, #data th {
border: 1px solid #ddd;
padding: 8px;
}
#data tr:nth-child(even){background-color: #f2f2f2;}
#data tr:hover {background-color: #ddd;}
#data th {
padding-top: 12px;
padding-bottom: 12px;
text-align: left;
background-color: #4CAF50;
color: white;
}
</style><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>{0}</p><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Operating Conditions</p><table id="data">
<thead><tr><th>Parameter</th><th>Min</th><th>Typ</th><th>Max</th><th>Units</th></tr></thead>
<tbody>
<tr><td>Power supply (VDD) range</td><td>25</td><td>25</td><td>25</td><td>Volts</td></tr>
<tr><td>Operating Temperature</td><td>5.0</td><td>5.0</td><td>5.0</td><td>Celsius</td></tr>
<tr><td>Operating Frequency (F)</td><td></td><td></td><td>213</td><td>MHz</td></tr>
</tbody>
</table><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Timing and Current Data</p><table id="data">
<thead><tr><th>Parameter</th><th>Min</th><th>Max</th><th>Units</th></tr></thead>
<tbody>
<tr><td>1</td><td>2</td><td>3</td><td>4</td></tr>
</tbody>
</table><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Characterization Corners</p><table id="data">
<thead><tr><th>Corner Name</th><th>Process</th><th>Power Supply</th><th>Temperature</th><th>Library Name Suffix</th></tr></thead>
<tbody>
<tr><td>TT</td><td>Typical - Typical</td><td>25</td><td>5.0</td><td>_TT_5p0V_25C.lib</td></tr>
</tbody>
</table><p style=font-size: 20px;font-family: "Trebuchet MS", Arial, Helvetica, sans-serif;>Deliverables</p><table id="data">
<thead><tr><th>Type</th><th>Description</th><th>Link</th></tr></thead>
<tbody>
<tr><td>.sp</td><td>SPICE netlists</td><td><a href="file:///home/jesse/clones/PrivateRAM/compiler/./designdir/testsram/sram_2_16_1_scn4m_subm.sp">sram_2_16_1_scn4m_subm.sp</a></td></tr>
<tr><td>.v</td><td>Verilog simulation models</td><td><a href="file:///home/jesse/clones/PrivateRAM/compiler/./designdir/testsram/sram_2_16_1_scn4m_subm.v">sram_2_16_1_scn4m_subm.v</a></td></tr>
<tr><td>.gds</td><td>GDSII layout views</td><td><a href="file:///home/jesse/clones/PrivateRAM/compiler/./designdir/testsram/sram_2_16_1_scn4m_subm.gds">sram_2_16_1_scn4m_subm.gds</a></td></tr>
<tr><td>.lef</td><td>LEF files</td><td><a href="file:///home/jesse/clones/PrivateRAM/compiler/./designdir/testsram/sram_2_16_1_scn4m_subm.lef">sram_2_16_1_scn4m_subm.lef</a></td></tr>
<tr><td>.lib</td><td>Synthesis models</td><td><a href="file:///home/jesse/clones/PrivateRAM/compiler/./designdir/testsram/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib">sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib</a></td></tr>
</tbody>
</table>