mirror of https://github.com/VLSIDA/OpenRAM.git
Reduce verbosity of level 1 debug.
This commit is contained in:
Matt Guthaus
parent
f8e761313a
commit
a3666d82ab
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@ -114,7 +114,7 @@ class router(router_tech):
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self.all_pins.update(pin_set)
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for pin in self.pins[pin_name]:
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debug.info(2,"Retrieved pin {}".format(str(pin)))
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debug.info(3,"Retrieved pin {}".format(str(pin)))
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@ -123,6 +123,8 @@ class router(router_tech):
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Finds the pin shapes and converts to tracks.
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Pin can either be a label or a location,layer pair: [[x,y],layer].
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"""
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debug.info(1,"Finding pins for {}.".format(pin_name))
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self.retrieve_pins(pin_name)
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self.analyze_pins(pin_name)
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@ -133,6 +135,7 @@ class router(router_tech):
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This doesn't consider whether the obstacles will be pins or not. They get reset later
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if they are not actually a blockage.
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"""
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debug.info(1,"Finding blockages.")
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for layer in [self.vert_layer_number,self.horiz_layer_number]:
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self.retrieve_blockages(layer)
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@ -203,15 +206,15 @@ class router(router_tech):
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if pg1.adjacent(pg2):
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combined = pin_group(pin_name, [], self)
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combined.combine_groups(pg1, pg2)
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debug.info(2,"Combining {0} {1} {2}:".format(pin_name, index1, index2))
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debug.info(2, " {0}\n {1}".format(pg1.pins, pg2.pins))
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debug.info(2," --> {0}\n {1}".format(combined.pins,combined.grids))
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debug.info(3,"Combining {0} {1} {2}:".format(pin_name, index1, index2))
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debug.info(3, " {0}\n {1}".format(pg1.pins, pg2.pins))
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debug.info(3," --> {0}\n {1}".format(combined.pins,combined.grids))
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remove_indices.update([index1,index2])
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pin_groups.append(combined)
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break
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# Remove them in decreasing order to not invalidate the indices
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debug.info(2,"Removing {}".format(sorted(remove_indices)))
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debug.info(4,"Removing {}".format(sorted(remove_indices)))
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for i in sorted(remove_indices, reverse=True):
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del pin_groups[i]
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@ -228,7 +231,7 @@ class router(router_tech):
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Make multiple passes of the combine adjacent pins until we have no
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more combinations or hit an iteration limit.
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"""
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debug.info(1,"Combining adjacent pins for {}.".format(pin_name))
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# Start as None to signal the first iteration
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num_removed_pairs = None
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@ -245,6 +248,7 @@ class router(router_tech):
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This will try to separate all grid pins by the supplied number of separation
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tracks (default is to prevent adjacency).
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"""
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debug.info(1,"Separating adjacent pins.")
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# Commented out to debug with SCMOS
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#if separation==0:
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# return
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@ -270,7 +274,7 @@ class router(router_tech):
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grids_g1, grids_g2 = pg1.adjacent_grids(pg2, separation)
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# These should have the same length, so...
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if len(grids_g1)>0:
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debug.info(1,"Adjacent grids {0} {1} {2} {3}".format(index1,grids_g1,index2,grids_g2))
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debug.info(3,"Adjacent grids {0} {1} {2} {3}".format(index1,grids_g1,index2,grids_g2))
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self.remove_adjacent_grid(pg1, grids_g1, pg2, grids_g2)
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def remove_adjacent_grid(self, pg1, grids1, pg2, grids2):
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@ -292,12 +296,12 @@ class router(router_tech):
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# First, see if we can remove grids that are in the secondary grids
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# i.e. they aren't necessary to the pin grids
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if bigger_grids.issubset(bigger.secondary_grids):
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debug.info(1,"Removing {} from bigger {}".format(str(bigger_grids), bigger))
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debug.info(3,"Removing {} from bigger {}".format(str(bigger_grids), bigger))
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bigger.grids.difference_update(bigger_grids)
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self.blocked_grids.update(bigger_grids)
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return
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elif smaller_grids.issubset(smaller.secondary_grids):
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debug.info(1,"Removing {} from smaller {}".format(str(smaller_grids), smaller))
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debug.info(3,"Removing {} from smaller {}".format(str(smaller_grids), smaller))
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smaller.grids.difference_update(smaller_grids)
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self.blocked_grids.update(smaller_grids)
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return
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@ -426,7 +430,7 @@ class router(router_tech):
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def convert_blockages(self):
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""" Convert blockages to grid tracks. """
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debug.info(1,"Converting blockages.")
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for blockage in self.blockages:
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debug.info(3,"Converting blockage {}".format(str(blockage)))
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blockage_list = self.convert_blockage(blockage)
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@ -684,6 +688,7 @@ class router(router_tech):
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"""
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Convert the pin groups into pin tracks and blockage tracks.
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"""
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debug.info(1,"Converting pins for {}.".format(pin_name))
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for pg in self.pin_groups[pin_name]:
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pg.convert_pin()
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@ -733,7 +738,7 @@ class router(router_tech):
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debug.check(index<self.num_pin_components(pin_name),"Pin component index too large.")
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pin_in_tracks = self.pin_groups[pin_name][index].grids
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debug.info(1,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
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debug.info(2,"Set source: " + str(pin_name) + " " + str(pin_in_tracks))
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self.rg.add_source(pin_in_tracks)
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def add_path_target(self, paths):
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@ -752,7 +757,7 @@ class router(router_tech):
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debug.check(index<self.num_pin_grids(pin_name),"Pin component index too large.")
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pin_in_tracks = self.pin_groups[pin_name][index].grids
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debug.info(1,"Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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debug.info(2,"Set target: " + str(pin_name) + " " + str(pin_in_tracks))
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self.rg.add_target(pin_in_tracks)
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@ -760,7 +765,7 @@ class router(router_tech):
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"""
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Block all of the pin components.
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"""
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debug.info(2,"Setting blockages {0} {1}".format(pin_name,value))
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debug.info(3,"Setting blockages {0} {1}".format(pin_name,value))
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for pg in self.pin_groups[pin_name]:
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self.set_blockages(pg.grids, value)
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@ -796,7 +801,7 @@ class router(router_tech):
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"""
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path=self.prepare_path(path)
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debug.info(1,"Adding route: {}".format(str(path)))
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debug.info(2,"Adding route: {}".format(str(path)))
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# If it is only a square, add an enclosure to the track
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if len(path)==1:
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self.add_single_enclosure(path[0][0])
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@ -37,7 +37,7 @@ class router_tech:
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self.track_widths = [self.track_width] * 2
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self.track_factor = [1/self.track_width] * 2
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debug.info(1,"Track factor: {0}".format(self.track_factor))
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debug.info(2,"Track factor: {0}".format(self.track_factor))
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# When we actually create the routes, make them the width of the track (minus 1/2 spacing on each side)
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self.layer_widths = [self.track_width - self.horiz_layer_spacing, 1, self.track_width - self.vert_layer_spacing]
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@ -218,7 +218,7 @@ class supply_router(router):
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ur = grid_utils.get_upper_right(rail)
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z = ll.z
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pin = self.compute_wide_enclosure(ll, ur, z, name)
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debug.info(1,"Adding supply rail {0} {1}->{2} {3}".format(name,ll,ur,pin))
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debug.info(2,"Adding supply rail {0} {1}->{2} {3}".format(name,ll,ur,pin))
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self.cell.add_layout_pin(text=name,
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layer=pin.layer,
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offset=pin.ll(),
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@ -387,6 +387,7 @@ class supply_router(router):
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Route the horizontal and vertical supply rails across the entire design.
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Must be done with lower left at 0,0
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"""
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debug.info(1,"Routing supply rail {0}.".format(name))
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# Compute the grid locations of the supply rails
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self.compute_supply_rails(name, supply_number)
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@ -420,14 +421,14 @@ class supply_router(router):
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"""
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remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name])
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debug.info(1,"Pin {0} has {1} remaining components to route.".format(pin_name,
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remaining_components))
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debug.info(1,"Routing {0} with {1} pin components to route.".format(pin_name,
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remaining_components))
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for index,pg in enumerate(self.pin_groups[pin_name]):
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if pg.is_routed():
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continue
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debug.info(2,"Routing component {0} {1}".format(pin_name, index))
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debug.info(3,"Routing component {0} {1}".format(pin_name, index))
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# Clear everything in the routing grid.
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self.rg.reinit()
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@ -453,7 +454,7 @@ class supply_router(router):
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"""
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Add the supply rails of given name as a routing target.
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"""
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debug.info(2,"Add supply rail target {}".format(pin_name))
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debug.info(4,"Add supply rail target {}".format(pin_name))
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# Add the wire itself as the target
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self.rg.set_target(self.supply_rail_wire_tracks[pin_name])
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# But unblock all the rail tracks including the space
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@ -464,7 +465,7 @@ class supply_router(router):
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"""
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Add the supply rails of given name as a routing target.
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"""
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debug.info(3,"Blocking supply rail")
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debug.info(4,"Blocking supply rail")
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for rail_name in self.supply_rail_tracks:
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self.rg.set_blocked(self.supply_rail_tracks[rail_name])
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