Added scn4m_subm.

Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.

compiler/tests/config_20_scn4m_subm.py

@@ -0,0 +1,9 @@
+word_size = 1
+num_words = 16
+num_banks = 1
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+

technology/scn3me_subm/tech/tech.py

@@ -157,7 +157,7 @@ drc["minarea_metal1"] = 0
 # 8.1 Exact size 
 drc["minwidth_via1"] = 2*_lambda_
 # 8.2 Minimum via1 spacing 
-drc["via1_to_via1"] = 2*_lambda_
+drc["via1_to_via1"] = 3*_lambda_
 
 # 9.1 Minimum width
 drc["minwidth_metal2"] = 3*_lambda_

technology/scn4m_subm/mag_lib/.magicrc

@@ -0,0 +1,5 @@
+path sys +$::env(OPENRAM_TECH)/scn4m_subm/tech
+tech load SCN4M_SUBM.20 -noprompt
+scalegrid 1 4
+set GND gnd
+set VDD vdd

technology/scn4m_subm/mag_lib/convertall.sh

@@ -0,0 +1,14 @@
+magic -dnull -noconsole << EOF
+load dff
+gds write dff.gds
+load cell_6t
+gds write cell_6t.gds
+load replica_cell_6t
+gds write replica_cell_6t.gds
+load sense_amp
+gds write sense_amp.gds
+load tri_gate
+gds write tri_gate.gds
+load write_driver
+gds write write_driver.gds
+EOF

technology/scn4m_subm/sp_lib/dff.sp

@@ -14,7 +14,7 @@ M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
 M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
 M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
 M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
-M1010 gnd clk a_24_24# gnd nfet w=4u l=0.4u
+M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
 M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
 M1012 a_84_24# D gnd gnd n w=2u l=0.4u
 M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u

technology/scn4m_subm/tech/tech.py

@@ -159,7 +159,7 @@ drc["minarea_metal1"] = 0
 # 8.1 Exact size 
 drc["minwidth_via1"] = 2*_lambda_
 # 8.2 Minimum via1 spacing 
-drc["via1_to_via1"] = 2*_lambda_
+drc["via1_to_via1"] = 3*_lambda_
 
 # 9.1 Minimum width
 drc["minwidth_metal2"] = 3*_lambda_
@@ -176,7 +176,7 @@ drc["metal2_enclosure_via2"] = _lambda_
 # Not a rule
 drc["minarea_metal2"] = 0
 
-# 14.2 Exact size
+# 14.1 Exact size
 drc["minwidth_via2"] = 2*_lambda_
 # 14.2 Minimum spacing
 drc["via2_to_via2"] = 3*_lambda_
@@ -188,13 +188,13 @@ drc["metal3_to_metal3"] = 3*_lambda_
 # 15.3 Minimum overlap of via 2
 drc["metal3_extend_via2"] = _lambda_
 # Reserved for asymmetric enclosures
-drc["metal3_enclosure_via2"] = 2*_lambda_
+drc["metal3_enclosure_via2"] = _lambda_
 # Reserved for asymmetric enclosures
 drc["metal2_enclosure_via1"] = _lambda_
 # 21.3 Minimum overlap by metal3
-drc["metal3_extend_via2"] = _lambda_
+drc["metal3_extend_via3"] = _lambda_
 # Reserved for asymmetric enclosures
-drc["metal3_enclosure_via2"] = _lambda_
+drc["metal3_enclosure_via3"] = _lambda_
 # Not a rule
 drc["minarea_metal3"] = 0
 
@@ -204,13 +204,13 @@ drc["minwidth_via3"] = 2*_lambda_
 drc["via3_to_via3"] = 3*_lambda_
 
 # 22.1 Minimum width
-drc["minwidth_metal3"] = 6*_lambda_
-# 22.2 Minimum spacing to metal3
-drc["metal3_to_metal3"] = 6*_lambda_
-# 22.3 Minimum overlap of via 2
-drc["metal3_extend_via2"] = 2*_lambda_
+drc["minwidth_metal4"] = 6*_lambda_
+# 22.2 Minimum spacing to metal4
+drc["metal4_to_metal4"] = 6*_lambda_
+# 22.3 Minimum overlap of via 3
+drc["metal4_extend_via3"] = 2*_lambda_
 # Reserved for asymmetric enclosures
-drc["metal3_enclosure_via2"] = 2*_lambda_
+drc["metal4_enclosure_via3"] = 2*_lambda_
 # Not a rule
 drc["minarea_metal3"] = 0
 

technology/scn4me_subm/mag_lib/.magicrc

@@ -1,5 +0,0 @@
-path sys +$::env(OPENRAM_TECH)/scn4me_subm/tech
-tech load SCN4ME_SUBM.20 -noprompt
-scalegrid 1 4
-set GND gnd
-set VDD vdd

technology/setup_scripts/setup_openram_scn4m_subm.py

@@ -0,0 +1,41 @@
+#!/usr/bin/python
+"""
+This type of setup script should be placed in the setup_scripts directory in the trunk
+"""
+
+import sys
+import os
+
+TECHNOLOGY = "scn4m_subm"
+
+
+##########################
+# CDK paths
+
+# os.environ["CDK_DIR"] = CDK_DIR #PDK path
+# os.environ["SYSTEM_CDS_LIB_DIR"] = "{0}/cdssetup".format(CDK_DIR) 
+# os.environ["CDS_SITE"] = CDK_DIR 
+os.environ["MGC_TMPDIR"] = "/tmp" 
+
+###########################
+# OpenRAM Paths
+
+    
+try:
+    DRCLVS_HOME = os.path.abspath(os.environ.get("DRCLVS_HOME"))
+except:
+    OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
+    DRCLVS_HOME=OPENRAM_TECH+"/scn4m_subm/tech"
+os.environ["DRCLVS_HOME"] = DRCLVS_HOME
+
+# try:
+#     SPICE_MODEL_DIR = os.path.abspath(os.environ.get("SPICE_MODEL_DIR"))
+# except:
+OPENRAM_TECH=os.path.abspath(os.environ.get("OPENRAM_TECH"))
+os.environ["SPICE_MODEL_DIR"] = "{0}/{1}/models".format(OPENRAM_TECH, TECHNOLOGY)
+
+##########################
+# Paths required for OPENRAM to function
+
+LOCAL = "{0}/..".format(os.path.dirname(__file__)) 
+sys.path.append("{0}/{1}/tech".format(LOCAL,TECHNOLOGY))