mirror of https://github.com/VLSIDA/OpenRAM.git
Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test.
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fd806077d2
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@ -111,6 +111,7 @@ class trim_spice():
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match of the line with a term so you can search for a single
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net connection, the instance name, anything..
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"""
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removed_insts = 0
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#Expects keep_inst_list are regex patterns. Compile them here.
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compiled_patterns = [re.compile(pattern) for pattern in keep_inst_list]
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@ -127,11 +128,14 @@ class trim_spice():
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new_buffer.append(line)
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in_subckt=False
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elif in_subckt:
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removed_insts += 1
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for pattern in compiled_patterns:
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if pattern.search(line) != None:
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new_buffer.append(line)
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removed_insts -= 1
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break
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else:
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new_buffer.append(line)
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self.sp_buffer = new_buffer
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debug.info(2, "Removed {} instances from {} subcircuit.".format(removed_insts, subckt_name))
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File diff suppressed because it is too large
Load Diff
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@ -86,7 +86,6 @@ class sram():
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# Save the extracted spice file
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if OPTS.use_pex:
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import verify
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print(verify.__file__)
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start_time = datetime.datetime.now()
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# Output the extracted design if requested
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sp_file = OPTS.output_path + "temp_pex.sp"
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@ -11,13 +11,17 @@ import globals
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from globals import OPTS
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import debug
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@unittest.skip("SKIPPING 27_worst_case_delay_test")
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class worst_case_timing_sram_test(openram_test):
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def runTest(self):
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OPTS.tech_name = "freepdk45"
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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OPTS.spice_name="ngspice"
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OPTS.spice_name="hspice"
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OPTS.analytical_delay = False
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OPTS.trim_netlist = False
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OPTS.check_lvsdrc = True
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# This is a hack to reload the characterizer __init__ with the spice version
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from importlib import reload
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@ -27,21 +31,36 @@ class worst_case_timing_sram_test(openram_test):
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if not OPTS.spice_exe:
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debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
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word_size, num_words, num_banks = 32, 32, 1
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from sram import sram
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from sram_config import sram_config
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c = sram_config(word_size=4,
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num_words=32,
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num_banks=1)
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c.words_per_row=1
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debug.info(1, "Testing the timing for 2 bits inside a 2bit, 16words SRAM with 1 bank")
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c = sram_config(word_size=word_size,
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num_words=num_words,
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num_banks=num_banks)
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#c.words_per_row=1
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c.compute_sizes()
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debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
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word_size, num_words, num_banks))
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s = sram(c, name="sram1")
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tempspice = OPTS.openram_temp + "temp.sp"
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s.sp_write(tempspice)
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sp_netlist_file = OPTS.openram_temp + "temp.sp"
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s.sp_write(sp_netlist_file)
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if OPTS.use_pex:
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gdsname = OPTS.output_path + s.name + ".gds"
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s.gds_write(gdsname)
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import verify
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reload(verify)
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# Output the extracted design if requested
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sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
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verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
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sp_sim_file = sp_pex_file
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else:
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sp_sim_file = sp_netlist_file
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corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
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wc = worst_case(s.s, tempspice, corner)
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wc = worst_case(s.s, sp_sim_file, corner)
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import tech
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loads = [tech.spice["msflop_in_cap"]*4]
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slews = [tech.spice["rise_time"]*2]
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Binary file not shown.
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@ -54,7 +54,6 @@ else:
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if OPTS.pex_exe == None:
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from .none import run_pex,print_pex_stats
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print("why god why")
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elif "calibre"==OPTS.pex_exe[0]:
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from .calibre import run_pex,print_pex_stats
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elif "magic"==OPTS.pex_exe[0]:
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