Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test.

This commit is contained in:
Hunter Nichols 2018-10-08 15:45:54 -07:00
parent fd806077d2
commit a3bec5518c
6 changed files with 43 additions and 992 deletions

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@ -111,6 +111,7 @@ class trim_spice():
match of the line with a term so you can search for a single
net connection, the instance name, anything..
"""
removed_insts = 0
#Expects keep_inst_list are regex patterns. Compile them here.
compiled_patterns = [re.compile(pattern) for pattern in keep_inst_list]
@ -127,11 +128,14 @@ class trim_spice():
new_buffer.append(line)
in_subckt=False
elif in_subckt:
removed_insts += 1
for pattern in compiled_patterns:
if pattern.search(line) != None:
new_buffer.append(line)
removed_insts -= 1
break
else:
new_buffer.append(line)
self.sp_buffer = new_buffer
debug.info(2, "Removed {} instances from {} subcircuit.".format(removed_insts, subckt_name))

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@ -86,7 +86,6 @@ class sram():
# Save the extracted spice file
if OPTS.use_pex:
import verify
print(verify.__file__)
start_time = datetime.datetime.now()
# Output the extracted design if requested
sp_file = OPTS.output_path + "temp_pex.sp"

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@ -11,13 +11,17 @@ import globals
from globals import OPTS
import debug
@unittest.skip("SKIPPING 27_worst_case_delay_test")
class worst_case_timing_sram_test(openram_test):
def runTest(self):
OPTS.tech_name = "freepdk45"
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
OPTS.spice_name="ngspice"
OPTS.spice_name="hspice"
OPTS.analytical_delay = False
OPTS.trim_netlist = False
OPTS.check_lvsdrc = True
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
@ -27,21 +31,36 @@ class worst_case_timing_sram_test(openram_test):
if not OPTS.spice_exe:
debug.error("Could not find {} simulator.".format(OPTS.spice_name),-1)
word_size, num_words, num_banks = 32, 32, 1
from sram import sram
from sram_config import sram_config
c = sram_config(word_size=4,
num_words=32,
num_banks=1)
c.words_per_row=1
debug.info(1, "Testing the timing for 2 bits inside a 2bit, 16words SRAM with 1 bank")
c = sram_config(word_size=word_size,
num_words=num_words,
num_banks=num_banks)
#c.words_per_row=1
c.compute_sizes()
debug.info(1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank".format(
word_size, num_words, num_banks))
s = sram(c, name="sram1")
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
sp_netlist_file = OPTS.openram_temp + "temp.sp"
s.sp_write(sp_netlist_file)
if OPTS.use_pex:
gdsname = OPTS.output_path + s.name + ".gds"
s.gds_write(gdsname)
import verify
reload(verify)
# Output the extracted design if requested
sp_pex_file = OPTS.output_path + s.name + "_pex.sp"
verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file)
sp_sim_file = sp_pex_file
else:
sp_sim_file = sp_netlist_file
corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
wc = worst_case(s.s, tempspice, corner)
wc = worst_case(s.s, sp_sim_file, corner)
import tech
loads = [tech.spice["msflop_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]

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@ -54,7 +54,6 @@ else:
if OPTS.pex_exe == None:
from .none import run_pex,print_pex_stats
print("why god why")
elif "calibre"==OPTS.pex_exe[0]:
from .calibre import run_pex,print_pex_stats
elif "magic"==OPTS.pex_exe[0]: