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1839 Commits

Author SHA1 Message Date
Matt Guthaus beceb3fb60 Fix buggy analytical delay in pdriver 2019-01-25 16:22:59 -08:00
Matt Guthaus 01ab253925 Move gdsMill license to README 2019-01-25 15:56:12 -08:00
Matt Guthaus d2864370aa Temporarily disable abort on supply error 2019-01-25 15:43:57 -08:00
Matt Guthaus 09d6a63861 Change path to wire_path for Anaconda package conflict 2019-01-25 15:07:56 -08:00
Matt Guthaus 0c3baa5172 Added some comments to the spice files. 2019-01-25 15:00:00 -08:00
Matt Guthaus 1afd4341bd Update stage effort of clk_buf_driver 2019-01-25 14:22:37 -08:00
Matt Guthaus 6f32bac1a2 Use rx of last pdriver instance after placing instances 2019-01-25 14:17:37 -08:00
Matt Guthaus 614aa54f17 Move clkbuf output lower to avoid dff outputs 2019-01-25 14:03:52 -08:00
Matt Guthaus ddf734891a Fix pdriver width error 2019-01-25 10:26:31 -08:00
Matt Guthaus 8f56953af0 Convert wordline driver to use sized pdriver 2019-01-24 10:20:23 -08:00
Hunter Nichols ee03b4ecb8 Added some data variation checking 2019-01-24 09:25:09 -08:00
Jesse Cirimelli-Low 65c5cc9fe7 added support for more corner variations 2019-01-24 07:09:51 -08:00
Matt Guthaus 091b4e4c62 Add size commments to spize. Change pdriver stage effort. 2019-01-23 17:27:15 -08:00
Hunter Nichols d527b7da62 Added delay error calculations 2019-01-23 13:19:35 -08:00
Matt Guthaus 8a85d3141a Fix polarity problem. 2019-01-23 13:08:43 -08:00
Matt Guthaus d64d262d78 Fix pdriver instantiation. Change sizes based on word_size. 2019-01-23 12:51:28 -08:00
Matt Guthaus b58fd03083 Change pbuf/pinv to pdriver in control logic. 2019-01-23 12:03:52 -08:00
Hunter Nichols 6d3884d60d Added corner data collection. 2019-01-22 16:40:46 -08:00
Jesse Cirimelli-Low ac17e71973 removed debug print statement 2019-01-22 15:47:16 -08:00
Jesse Cirimelli-Low 886dd4d313 Merge branch 'dev' into datasheet_gen 2019-01-22 15:24:44 -08:00
Jesse Cirimelli-Low 978990f4dd cleaned up debug.py edits 2019-01-22 15:24:38 -08:00
Matt Guthaus 23718b952f Check for print statements in more files since we now use print_raw 2019-01-18 10:16:55 -08:00
Matt Guthaus f5f27073be Merge remote-tracking branch 'origin/dev' into factory 2019-01-18 09:52:18 -08:00
Hunter Nichols 5885e3b635 Removed carriage returns, adjusted signal names generation for variable delay chain size. 2019-01-18 00:23:50 -08:00
Yusu Wang c20fb2a70e replace matrix to array 2019-01-17 12:01:08 -08:00
Hunter Nichols 4ced6be6bd Added data collection and some initial data 2019-01-17 09:54:34 -08:00
Hunter Nichols 5bbc43d0a0 Added data collection of wordline and s_en measurements. 2019-01-17 01:59:41 -08:00
Jesse Cirimelli-Low 9c8090d94b added debug.info to logging 2019-01-16 19:56:23 -08:00
Matt Guthaus 7a152ea13d Move sram_factory to root dir 2019-01-16 17:06:29 -08:00
Matt Guthaus 9ecfaf16ea Add the factory class 2019-01-16 17:04:28 -08:00
Matt Guthaus 91636be642 Convert all contacts to use the sram_factory 2019-01-16 16:56:06 -08:00
Matt Guthaus 5192a01f2d Convert pgates to use ptx through the factory 2019-01-16 16:30:31 -08:00
Matt Guthaus a418431a42 First draft of sram_factory code 2019-01-16 16:15:38 -08:00
Jesse Cirimelli-Low 25b0da404f removed EOL error in comment 2019-01-16 16:08:41 -08:00
Jesse Cirimelli-Low 41b8e8665b updated datasheet descriptors 2019-01-16 15:43:08 -08:00
Jesse Cirimelli-Low 0556b86424 html datasheet no longer dependeds on sram 2019-01-16 14:52:01 -08:00
Jesse Cirimelli-Low 192c615a38 moved library page to new repo 2019-01-16 07:33:17 -08:00
Hunter Nichols cc0be510c7 Added some data scaling and error calculation in model check. 2019-01-16 00:46:24 -08:00
Jesse Cirimelli-Low 813a551691 comment parsing 1/2 complete; page gen setup complete 2019-01-15 20:48:20 -08:00
Jesse Cirimelli-Low 903cafb336 html parsing finished 2019-01-15 19:47:48 -08:00
Hunter Nichols 6152ec7ec5 Merge branch 'dev' into multiport_characterization 2019-01-15 16:33:39 -08:00
Jesse Cirimelli-Low b66c53a99a added log file to datasheet 2019-01-13 15:02:13 -08:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus e210ef2a41 Add assert to lef and verilog unit test. Fix verilog files in golden results. 2019-01-11 16:42:50 -08:00
Matt Guthaus a7dd62b0e5 falling_edge not negative_edge 2019-01-11 15:17:27 -08:00
Matt Guthaus 20b869f8e1 Remove tabs 2019-01-11 14:16:57 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Matt Guthaus f0ab155172 Change dout to negative clock edge relative 2019-01-11 09:51:05 -08:00
Hunter Nichols 21663439cc Added slews measurements to the model checker. Removed unused code in bitline delay class. 2019-01-09 22:42:34 -08:00
Jesse Cirimelli-Low a25e0f6c8c Merge branch 'dev' into datasheet_gen 2019-01-09 13:48:43 -08:00
Matt Guthaus cdef5f0ecb Change kbits to bits in output 2019-01-09 16:57:12 -08:00
Matt Guthaus be9f81768d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2019-01-09 15:20:34 -08:00
Matt Guthaus 94a6cbc28b Remove extra bracket in pin blokc 2019-01-09 13:44:25 -08:00
Jesse Cirimelli-Low b0978e62f3 removed openram placeholder logo to stage for public push 2019-01-09 12:32:17 -08:00
Matt Guthaus 49d0b9d69c Remove old scn3me golden results. Remove indices from new golden results. 2019-01-09 12:04:17 -08:00
Matt Guthaus fe077a453a Change capitalization of message to be consistent 2019-01-09 12:00:14 -08:00
Matt Guthaus 7e635d02be Remove indices from pins in lib file 2019-01-09 12:00:00 -08:00
Matt Guthaus 4d0a8b9c8a Check for coverage executable and run without if not found. 2019-01-09 08:24:20 -08:00
Jesse Cirimelli-Low e9b8eab2c3 Merge branch 'dev' into datasheet_gen 2019-01-09 06:16:09 -08:00
Jesse Cirimelli-Low 8b8985dbd1 track table_gen 2019-01-09 06:15:22 -08:00
Jesse Cirimelli-Low 3f8628fa94 flask totally purged, fixed table headers 2019-01-08 20:04:30 -08:00
Jesse Cirimelli-Low e58515b89b tables stable and flask removed, headers are bugged 2019-01-08 19:50:47 -08:00
Jesse Cirimelli-Low 6033cc604d stable, but incomplete flaskless table gen rewrite 2019-01-08 18:54:20 -08:00
Jesse Cirimelli-Low 19a986c35c no-flask rewrite for initial datasheet case complete 2019-01-07 19:43:57 -08:00
Jesse Cirimelli-Low 24161a1df2 Merge branch 'dev' into datasheet_gen 2019-01-07 18:18:46 -08:00
Jesse Cirimelli-Low 1283cbc3be fixed EOL error in descriptor 2019-01-07 18:17:38 -08:00
Jesse Cirimelli-Low 5508ae945d updated file html description to simplify parsing 2019-01-07 17:08:47 -08:00
Matt Guthaus 2236ca40df Make xa least priority since it fails functional tests. 2019-01-03 19:20:31 -08:00
Jesse Cirimelli-Low 6acc8c8902 removed print debug statement 2019-01-03 13:41:25 -08:00
Jesse Cirimelli-Low 53b7e46db4 fixed bug where retrieving git id would fail depending on cwd 2019-01-03 12:28:29 -08:00
Hunter Nichols 272267358f Moved all bitline delay measurements to delay class. Added measurements to check delay model. 2019-01-03 05:51:28 -08:00
Jesse Cirimelli-Low c69e5fdb18 added compile time to datasheet 2019-01-02 10:30:03 -08:00
Jesse Cirimelli-Low cc27736a45 moved DRC and LVS error reports to datasheet.info from datasheet.py 2019-01-02 10:14:45 -08:00
Hunter Nichols 66b2fcdc91 Added data parsing to measurement objects and adding power measurements. 2018-12-20 15:54:56 -08:00
Hunter Nichols b10ef3fb7e Replaced delay measure statement with object implementation. 2018-12-19 18:33:06 -08:00
Hunter Nichols 8eb4812e16 Made parasitic delay parameter in Freepdk45 more accurate, added stage names to delay model. 2018-12-17 23:32:02 -08:00
Hunter Nichols 51b1bd46da Added option to use delay chain size defined in tech.py 2018-12-14 18:02:19 -08:00
Hunter Nichols dc20bf9e11 Added bitline measurements to ngspice delay test. 2018-12-13 22:31:08 -08:00
Hunter Nichols e4065929c2 Added bitline threshold delay checks to delay tests. 2018-12-13 22:21:30 -08:00
Jennifer Eve Sowash 4a5c18b6cc Removed line to skip pdriver_test 2018-12-13 19:10:38 -08:00
Jennifer Eve Sowash bc44c80d40 Added height to init in pdriver.py 2018-12-13 19:03:31 -08:00
Hunter Nichols 97fc37aec1 Added checks for the bitline voltage at sense amp enable 50%. 2018-12-12 23:59:32 -08:00
Hunter Nichols 0510aeb3ec Merged with dev, removed commented out code. 2018-12-12 16:02:16 -08:00
Hunter Nichols 50f13eabce Added better port selection to bitline measurements. 2018-12-12 15:59:20 -08:00
Hunter Nichols 0a26e40022 Attempts to fix failing tests. Random seed differences between mada and pipeline. 2018-12-12 13:12:26 -08:00
Hunter Nichols 6ac474d642 Added bitline measures with hardcoded names. 2018-12-12 00:43:08 -08:00
Hunter Nichols 82e074ebf0 Added initial structure for bitline measurements. 2018-12-11 14:06:11 -08:00
Jennifer Eve Sowash a51aacfa90 Added corner case for 1 inv pos polarity and renamed variables. 2018-12-07 19:42:11 -08:00
Matt Guthaus 37c10a2198 Merge branch 'supply_routing' into dev 2018-12-07 17:04:37 -08:00
Matt Guthaus b15584a821 Print start time after banner and init 2018-12-07 15:50:18 -08:00
Hunter Nichols 4d84731c34 Edited heuristic delay chain and delay model to account for read port differences. 2018-12-07 15:39:53 -08:00
Matt Guthaus 3f468b1c18 Only print_time when not a unit test or debug_level set 2018-12-07 15:14:28 -08:00
Jennifer Eve Sowash d302f1cd0a Merge branch 'pdriver' into dev 2018-12-07 14:37:25 -08:00
Matt Guthaus 5248482fab Merge branch 'dev' into supply_routing 2018-12-07 14:28:49 -08:00
Matt Guthaus 6f171ad147 Added router timing code. Commented combine adjacent pins due to run-time complexity 2018-12-07 13:54:18 -08:00
Matt Guthaus 5ed9904855 Cast dict_values to a list for pin_groups 2018-12-07 13:02:50 -08:00
Jennifer Eve Sowash a6eec10f41 Passed freepdk45 tests with pdriver.py 2018-12-07 12:58:05 -08:00
Matt Guthaus dfb2cf3cbd Change analyze_pins to a heuristic algorithm less than O(n^2) 2018-12-07 12:41:32 -08:00
Jennifer Eve Sowash a24e5229cb Fixed method of determining inverter number. 2018-12-07 10:19:18 -08:00
Matt Guthaus a96f492d0a Add profile scripts 2018-12-07 08:56:40 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 5319107afa Skip pdriver test until LVS fix 2018-12-07 07:41:35 -08:00
Matt Guthaus d38d5a6d58 Merge branch 'supply_routing' into dev 2018-12-07 07:39:53 -08:00
Jennifer Eve Sowash 653ab3eda4 Changed method of determining number of inverters. 2018-12-06 19:34:19 -08:00
Jennifer Eve Sowash 8ea85e3e65 Merge branch 'dev' into pdriver 2018-12-06 14:38:08 -08:00
Jennifer Eve Sowash 5e19cf1e24 Updated naming, added compute_sizes(), and fixed sizing function. 2018-12-06 14:36:01 -08:00
Matt Guthaus 537e0689fb Add combine adjacent pins back 2018-12-06 14:29:06 -08:00
Matt Guthaus c51752d245 Provide more stats in -v output 2018-12-06 14:11:15 -08:00
Matt Guthaus 514f6fda27 Increase size for warning of column mux limit 2018-12-06 13:57:38 -08:00
Matt Guthaus 3f1fbc3d90 Merge remote-tracking branch 'origin' into supply_routing 2018-12-06 13:53:51 -08:00
Matt Guthaus c0295a2c3d Rewrite if/else to be correct and more legible. 2018-12-06 13:23:39 -08:00
Matt Guthaus 46d3068821 Output number of words per row before SRAM creation. Recompute words per row in unit tests. 2018-12-06 13:11:47 -08:00
Matt Guthaus 6f1af4d0c9 Remove extraneous m2m3 via that causes DRC 2018-12-06 12:45:45 -08:00
Matt Guthaus b5a7274316 Change Netlisting to submodules to reflect what time is of 2018-12-06 11:59:20 -08:00
Matt Guthaus e4c67875d2 Add non-minimum width metal2 in route when vias can be close 2018-12-06 11:58:57 -08:00
Matt Guthaus b7bbc9b994 Add output on number of ports. 2018-12-06 11:58:34 -08:00
Matt Guthaus b72382b400 Fix offset bug with negative vertical supply rails 2018-12-06 11:58:19 -08:00
Jesse Cirimelli-Low afb32ed834 removed outdated 'unknown' for analytical frequency 2018-12-06 10:29:48 -08:00
Jesse Cirimelli-Low bf27eb8cd6 removed placeholder data 2018-12-06 10:17:12 -08:00
Jesse Cirimelli-Low 1633ae0265 base64 encode images for portability 2018-12-06 10:13:28 -08:00
Jesse Cirimelli-Low 02b4b13cc4 fixed config file path 2018-12-06 09:26:38 -08:00
Jesse Cirimelli-Low e41b90449d specify config file abs path 2018-12-06 05:34:05 -08:00
Hunter Nichols b157fc58a1 Moved feasible period search from functional.py to tests. 2018-12-05 23:23:40 -08:00
Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds. 2018-12-05 20:43:10 -08:00
Hunter Nichols 448e8f4cfd Merged with dev 2018-12-05 17:49:42 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Matt Guthaus 7645a909eb Merge branch 'supply_routing' into dev 2018-12-05 17:24:51 -08:00
Hunter Nichols ea55bda493 Changed s_en delay calculation based recent control logic changes. 2018-12-05 17:10:11 -08:00
Jesse Cirimelli-Low 1dae539e1d track git_id 2018-12-05 16:13:52 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low 32bd91aafd track ORIG_HEAD file 2018-12-05 13:39:54 -08:00
Jesse Cirimelli-Low 7a20420030 get ORIG_HEAD with pre-commit hook 2018-12-05 13:38:09 -08:00
Matt Guthaus 2cd1322071 Clean up Makefile for unit tests 2018-12-05 12:58:10 -08:00
Matt Guthaus fa3bf2915a Remove commented code 2018-12-05 09:56:19 -08:00
Matt Guthaus 0c0a23e6eb Cleanup code. Add time breakdown for SRAM creation. 2018-12-05 09:51:17 -08:00
Hunter Nichols 0c3c58011b Fixed delay test values. 2018-12-05 00:13:23 -08:00
Matt Guthaus f1c74d6bfb Merge branch 'dev' into supply_routing 2018-12-04 17:57:18 -08:00
Matt Guthaus d95b34caf2 Round output to look pretty 2018-12-04 17:08:47 -08:00
Matt Guthaus e750d446dc Fix syntax error. Enable skipped test. 2018-12-04 17:08:22 -08:00
Matt Guthaus 126d4a8d10 Fix instersection bug. Improve primary and secondary pin algo. 2018-12-04 16:53:04 -08:00
Jesse Cirimelli-Low b6e7ddd023 Merge branch 'dev' into datasheet_gen 2018-12-04 16:27:04 -08:00
Matt Guthaus 7ce75398a8 Change warning to info 2018-12-04 09:42:47 -08:00
Matt Guthaus 7fce6f06ca Expand grids to maximal pin before removing blockages 2018-12-04 09:35:40 -08:00
Matt Guthaus 389bb91af4 Simplifying supply router to single grid track 2018-12-04 08:41:57 -08:00
Matt Guthaus 2a68b57215 Changed psram info to sram 2018-12-03 15:59:31 -08:00
Jesse Cirimelli-Low 2c12ef2161 added warning to test 30 coverage is not installed 2018-12-03 13:24:22 -08:00
Jennifer Eve Sowash 2534a32e20 pdriver.py passes resgression tests. Size and number of inverters has been added. 2018-12-03 12:55:48 -08:00
Jesse Cirimelli-Low 71bb1bb9f1 updated test 30 to dev version 2018-12-03 11:09:45 -08:00
Matt Guthaus c6f03e70d4 Convert supply to wider DRC rules 2018-12-03 11:09:17 -08:00
Jesse Cirimelli-Low c869c7e870 added tracking to new debug files 2018-12-03 10:54:50 -08:00
Jesse Cirimelli-Low 5646660765 added git id to datasheet 2018-12-03 10:53:50 -08:00
Jesse Cirimelli-Low 9501b99df7 merged branch wtih dev 2018-12-03 09:47:34 -08:00
Jennifer Eve Sowash da631618b6 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-12-03 09:14:13 -08:00
Matt Guthaus bcc6b95564 Add coverage exclusions. Add subprocess coverage. 2018-12-03 09:13:57 -08:00
Jennifer Sowash 887674aa85 Added pdriver.py for testing. 2018-12-03 09:11:12 -08:00
Hunter Nichols 722bc907c4 Merged with dev. Fixed conflicts in tests. 2018-12-02 23:09:00 -08:00
Matt Guthaus 49f7022416 Skip failing tests with comments for bugs. 2018-11-30 12:33:43 -08:00
Matt Guthaus 90d1fa7c43 Bitcell supply routing fixes. 
Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
 2018-11-30 12:32:13 -08:00
Matt Guthaus 7e054a51e2 Some techs don't need m1 power pins 2018-11-29 18:47:38 -08:00
Matt Guthaus 0af4263edb Remove extra rotated vias in bitcell array to simplify power routing 2018-11-29 18:13:15 -08:00
Matt Guthaus 0e7301fff8 Update unit test golden results. Skip two tests. 2018-11-29 17:28:57 -08:00
Matt Guthaus e98f7075e2 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-29 16:29:17 -08:00
Matt Guthaus 33a7683473 Remove used gated_clk instead of cs for read-only control logic. 2018-11-29 16:28:37 -08:00
Matt Guthaus a7be60529f Do not rotate vias in horizontal channel routes 2018-11-29 13:57:40 -08:00
Matt Guthaus 3c4d559308 Fixed syntax error referring to column mux 2018-11-29 13:29:16 -08:00
Matt Guthaus 3d3f54aa86 Add col addr line spacing for col addr decoder 2018-11-29 13:22:48 -08:00
Matt Guthaus 4df862d8af Convert channel router to take netlist of pins rather than names. 2018-11-29 12:12:10 -08:00
Matt Guthaus a7bc9e0de0 Use module height not instance uy for sram placement 2018-11-29 10:34:25 -08:00
Matt Guthaus 0a16d83181 Add more layout and functional port tests. 2018-11-29 10:28:43 -08:00
Matt Guthaus 14fa33e21d Remove 4 bank code and test for now. 2018-11-29 10:28:09 -08:00
Matt Guthaus 7054d0881a Fix col address dff spacing from bank. 2018-11-29 09:54:29 -08:00
Matt Guthaus 02a67f9867 Missing gap in port 1 col decoder 2018-11-28 18:07:31 -08:00
Matt Guthaus d041a498f3 Fix height of port 1 control bus. Adjust column decoder names. 2018-11-28 17:48:25 -08:00
Jesse Cirimelli-Low a4b1d2f13b added css style code 2018-11-28 17:21:50 -08:00
Jesse Cirimelli-Low 06805d1e70 file browser does not show files in root directory; removed test file 2018-11-28 17:18:59 -08:00
Matt Guthaus f8513da162 Remove local temp dir 2018-11-28 17:04:53 -08:00
Matt Guthaus a2a9cea37e Make column decoder same height as control to control and supply overlaps 2018-11-28 16:59:58 -08:00
Jesse Cirimelli-Low 79c4b3c4cd added files links 2018-11-28 16:56:24 -08:00
Matt Guthaus 3cfe74cefb Functional simulation uses threshold for high and low noise margins 2018-11-28 16:55:04 -08:00
Jesse Cirimelli-Low 44638cb885 jinja2 file browser working 2018-11-28 16:48:24 -08:00
Matt Guthaus 25ae3a5eae Fix error of no control bus width 2018-11-28 15:42:51 -08:00
Matt Guthaus d99dcd33e2 Fix SRAM level control routing errors. 2018-11-28 15:30:52 -08:00
Matt Guthaus 143e4ed7f9 Change hierchical decoder output order to match changes to netlist. 2018-11-28 14:09:45 -08:00
Matt Guthaus b5b691b73d Fix missing via in clk input of control 2018-11-28 13:20:39 -08:00
Matt Guthaus 2ed8fc1506 pgate inputs and outputs are all on M1 for flexible via placement when using gates. 2018-11-28 12:42:29 -08:00
Matt Guthaus 93904d9f2d Control logic passes DRC/LVS in SCMOS 2018-11-28 11:02:24 -08:00
Matt Guthaus 410115e830 Modify dff_buf to stagger Q and Qb outputs. 2018-11-28 10:43:11 -08:00
Matt Guthaus 25611fcbc1 Remove dff_inv since we can just use dff_buf 2018-11-28 10:42:22 -08:00
Matt Guthaus ea6abfadb7 Stagger outputs of dff_buf 2018-11-28 09:48:16 -08:00
Matt Guthaus d2ca2efdbe Limit ps, pd, as, ad precision in ptx. 2018-11-28 09:47:54 -08:00
Jesse Cirimelli-Low a56e3f609b removed debug print statements 2018-11-28 09:39:58 -08:00
Jesse Cirimelli-Low 0920321a2e start of static html generation code 2018-11-27 19:49:05 -08:00
Matt Guthaus c43a140b5e All control routed and DRC clean. LVS errors. 2018-11-27 17:18:03 -08:00
Matt Guthaus 5d59863efc Fix p_en_bar at top level. Change default scn4m period to 10ns. 2018-11-27 14:44:55 -08:00
Matt Guthaus c45f990413 Change en to en_bar in precharge. Fix logic for inverted p_en_bar. 2018-11-27 14:17:55 -08:00
Matt Guthaus 0c286d6c29 Revert to 5V example until we fix spice models in scn4m_subm 2018-11-27 14:17:06 -08:00
Jesse Cirimelli-Low 5aa8c46c16 Merge branch 'dev' into datasheet_gen 2018-11-27 13:54:21 -08:00
Matt Guthaus bf31126679 Correct decoder output numbers to follow address order 2018-11-27 12:03:13 -08:00
Matt Guthaus b912f289a6 Remove extra X in instance names 2018-11-27 12:02:53 -08:00
Matt Guthaus 2237af0463 Merge branch 'multiport_control_fix' of ssh://scone/home/mrg/openram into multiport_control_fix 2018-11-26 18:01:34 -08:00
Matt Guthaus cf23eacd0e Add wl_en 2018-11-26 18:00:59 -08:00
Matt Guthaus 21759d59b4 Remove inverter in wordline driver 2018-11-26 16:41:31 -08:00
Matt Guthaus 9e0b31d685 Make pand2 and pbuf derive pgate. Initial DRC wrong layout. 2018-11-26 16:19:18 -08:00
Matt Guthaus dd79fc560b Corretct modules for add_inst 2018-11-26 15:35:29 -08:00
Matt Guthaus b440031855 Add netlist only mode to new pgates 2018-11-26 15:29:42 -08:00
Matt Guthaus 2eff166527 Rotate vias in pand2 2018-11-26 14:05:04 -08:00
Matt Guthaus 5209619987 Move pnand2 output to allow input pin access on M2 2018-11-26 13:59:53 -08:00
Matt Guthaus 8fba32ca12 Add pand2 draft 2018-11-26 13:45:22 -08:00
Jennifer Eve Sowash 524334d24d Merge branch 'dev' into pdriver 2018-11-26 13:15:47 -08:00
Hunter Nichols b06aa84824 Functional tests now find a feasible period instead of using a heuristic. Bug found, trimming pbitcell netlists causes bit flips. 2018-11-23 18:55:15 -08:00
Hunter Nichols 5f954689a5 In delay.py, altered dummy address based on column mux. Added some hacks to make min_period work for srams with columns muxes. 2018-11-23 13:19:55 -08:00
Jennifer Eve Sowash bb7773ca7f Editted pbuf.py to pass regression. 2018-11-20 14:39:11 -08:00
Jesse Cirimelli-Low 29f19ad70f replaced absolute links with relative links 2018-11-20 12:27:54 -08:00
Jesse Cirimelli-Low 7d070c2652 Added links to logos 2018-11-20 11:51:38 -08:00
Hunter Nichols 67977bab3e Fixed port issue in bank. Changed golden data due to netlist change. 2018-11-20 11:39:14 -08:00
Jesse Cirimelli-Low 1942ef33ac Merge branch 'dev' into datasheet_gen 2018-11-20 11:23:42 -08:00
Hunter Nichols 62cbbca852 Merged, fixed conflict bt matching control logic creation to dev. 2018-11-19 22:20:20 -08:00
Hunter Nichols 2f29ad5510 Disabled resizing based on rise/fall delays. It creates delay chains which cannot be routed. 2018-11-19 22:13:58 -08:00
Matt Guthaus b8299565eb Use grid furthest from blockages when blocked pin. Enclose multiple connectors. 2018-11-19 17:32:55 -08:00
Hunter Nichols 8257e4fe8c Changed syntax in replica_bl tests, golden data to fit new values in delay tests. 2018-11-19 16:51:43 -08:00
Matt Guthaus 20d4e390f6 Add bounding box of connector for when there are multiple connectors 2018-11-19 15:45:07 -08:00
Matt Guthaus 2694ee1a4c Add all insufficient grids that overlap the pin at all 2018-11-19 15:43:19 -08:00
Hunter Nichols e8f1c19af6 Merge branch 'dev' into multiport_characterization 2018-11-19 15:42:48 -08:00
Matt Guthaus a47509de26 Move via away from cell edges 2018-11-19 15:42:22 -08:00
Hunter Nichols a55d907d03 High-to-low delays and slews are copied from the low-to-high values to simplify lib file results. FIXME 2018-11-19 15:40:26 -08:00
Matt Guthaus 6a7d721562 Add new bbox routine for pin enclosures 2018-11-19 09:28:29 -08:00
Matt Guthaus 4630f52de2 Use array ur instead of bank ur to pace row addr dff 2018-11-19 08:41:26 -08:00
Hunter Nichols d3c47ac976 Made delay measurements less dependent on period. 2018-11-18 23:28:49 -08:00
Matt Guthaus 7709d5caa7 Move row addr dffs to top of bank to prevent addr route problems 2018-11-18 10:02:08 -08:00
Matt Guthaus ba8bec3f67 Two m1 pitches at top of control logic 2018-11-18 09:30:27 -08:00
Matt Guthaus c677efa217 Fix control logic center location. Fix rail height error in write only control logic. 2018-11-18 09:15:03 -08:00
Hunter Nichols 3716030a23 Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts. 2018-11-16 16:57:22 -08:00
Matt Guthaus 047d6ca2ef Must channel rout the column mux bits since they could overlap 2018-11-16 16:21:31 -08:00
Matt Guthaus b89c011e41 Add psram 1w/1r test. Fix bl/br port naming errors in bank. 2018-11-16 15:31:22 -08:00
Matt Guthaus 8f28f4fde5 Don't always add all 3 types of contorl. Add write and read only port lists. 2018-11-16 15:03:12 -08:00
Matt Guthaus b13d938ea8 Add m3m4 short hand in design class 2018-11-16 14:10:49 -08:00
Matt Guthaus 4997a20511 Must set library cell flag for netlist only mode as well 2018-11-16 13:37:17 -08:00
Matt Guthaus ca750b698a Uniquify bitcell array 2018-11-16 12:52:22 -08:00
Matt Guthaus e040fd12f9 Bitcell and bitcell array can be named the same. 2018-11-16 12:00:23 -08:00
Matt Guthaus 5e0eb609da Check for single top-level structure in vlsiLayout. Don't allow dff_inv and dff_buf to have same names. 2018-11-16 11:48:41 -08:00
Matt Guthaus 68ac7e5955 Fix offset of column decoder with new mirroring 2018-11-15 17:27:58 -08:00
Matt Guthaus 712b71c5ca Mirror port 1 column decoder in X and Y 2018-11-15 15:26:59 -08:00
Jennifer Eve Sowash c73004de35 Merge branch 'pdriver' of https://github.com/VLSIDA/PrivateRAM into pdriver 2018-11-15 14:06:38 -08:00
Jesse Cirimelli-Low 59c0421804 merge dev into datasheet_gen; fixed merge conflict in hierarchy_design.py 2018-11-15 10:45:33 -08:00
Matt Guthaus 21d111acfe Move wordline driver clock line below decoder. Fix port 1 clock route DRC. 2018-11-15 10:30:38 -08:00
Hunter Nichols 6e47de3f9b Separated relative delay into rise/fall. 2018-11-14 23:34:53 -08:00
Matt Guthaus 66982a9283 Only add second port if it is specified. 2018-11-14 17:11:23 -08:00
Matt Guthaus 2fd86958a8 Merge branch 'multiport_layout' of ssh://scone/home/mrg/openram into multiport_layout 2018-11-14 17:07:01 -08:00
Matt Guthaus 3cfefa784f Fix run-time bug in combine adjacent pins for supply router 2018-11-14 17:06:12 -08:00
Matt Guthaus 3221d3e744 Add initial support and unit tests for 2 port SRAM 2018-11-14 17:05:23 -08:00
Hunter Nichols e9f6566e59 Fixed merge conflict, moved control logic mod instantiation, removed some commented out code. 2018-11-14 13:53:27 -08:00
Matt Guthaus 6ac5adaeca Separate multiport replica bitline from regular replica bitline test 2018-11-14 11:41:09 -08:00
Matt Guthaus 2f6300c7a0 Fix date/time formatting to remove fraction seconds. 2018-11-14 10:31:33 -08:00
Matt Guthaus 18d874a96a Fix error in iterative implementation of combine_classes 2018-11-14 10:05:04 -08:00
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell. 2018-11-13 22:24:18 -08:00
Matt Guthaus 4ebb8a26c4 Disable debug statements. 2018-11-13 17:43:08 -08:00
Matt Guthaus ddb4cabfe1 Change recursive equivalence class detection to iterative. 2018-11-13 17:42:06 -08:00
Matt Guthaus ff0a7851b7 Fix error when DRC is disabled so it doesn't initialize. 2018-11-13 17:41:32 -08:00
Jesse Cirimelli-Low fa27d647d2 Flask directory upload POC, embed datasheet.info in html comment for parser reuse 2018-11-13 17:29:43 -08:00
Matt Guthaus ce74827f24 Add new option to enable inline checks at each level of hierarchy. Default is off. 2018-11-13 16:51:19 -08:00
Matt Guthaus 01ceedb348 Only check number of ports when doing layout. 2018-11-13 16:42:25 -08:00
Matt Guthaus bc7e74f571 Add multiport bank test 2018-11-13 16:06:21 -08:00
Matt Guthaus aa779a7f82 Initial two port bank in SCMOS 2018-11-13 16:05:22 -08:00
Jennifer Sowash b6f1409fb9 Testing to ensure branch is up to date with dev. Added 04_pbuf_test.py and made changes to pbuf.py to align with comments. 2018-11-12 13:24:27 -08:00
Jennifer Sowash b366d88041 Merge branch 'dev' into pdriver 2018-11-12 11:30:37 -08:00
Jennifer Sowash 82abd32785 Added pbuf.py to create a single buffer. 2018-11-12 09:53:21 -08:00
Hunter Nichols 6f6d45f025 Merge branch 'dev' into multiport_characterization 2018-11-11 23:47:49 -08:00
Matt Guthaus 732f35a362 Change channel router to route from bottom up to simplify code. 2018-11-11 12:25:53 -08:00
Matt Guthaus 791d74f63a Fix wrong exception handling that depended on order. Replaced with if/else instead. 2018-11-11 12:02:42 -08:00
Jesse Cirimelli-Low 0dd97e54dd reverted css to UCSC colors, fixed header styling, added placeholder openram logo 2018-11-11 09:27:07 -08:00
Jesse Cirimelli-Low 4227a7886a Merge branch 'dev' into datasheet_gen 2018-11-11 07:27:42 -08:00
Jesse Cirimelli-Low 91a63fb5c2 Merge branch 'dev' 2018-11-11 07:24:03 -08:00
Jesse Cirimelli-Low 5c4ee911aa added another VLSI logo and fixed control port numbering 2018-11-11 07:22:13 -08:00
Jesse Cirimelli-Low aadf160ce4 added missing space in sheet 2018-11-11 06:05:14 -08:00
Jesse Cirimelli-Low 4ba07e4b94 Complete rewrite of parser, all ports (except clock) added on multiport sheets 2018-11-10 20:23:26 -08:00
Matt Guthaus 5cbbd5e4ca Comment out regress CI debug code 2018-11-10 13:44:36 -08:00
Matt Guthaus 6c17734712 Add testutil archive on failed tests for debug 2018-11-10 11:54:28 -08:00
Jesse Cirimelli-Low 62f8d26ec6 Merge branch 'dev' into datasheet_gen 2018-11-10 10:58:35 -08:00
Matt Guthaus 65b6bfd5e7 Change os to shutils 2018-11-10 10:06:33 -08:00
Matt Guthaus 3b6b93e2ca Save gds file in testutils when fail to figure out randomness in regression CI 2018-11-10 10:05:27 -08:00
Hunter Nichols bad55cfd05 Merged with dev. Fixed merge conflict. 2018-11-09 17:18:19 -08:00
Hunter Nichols ea1a1c7705 Added delay chain resizing based on analytical delay. 2018-11-09 17:14:52 -08:00
Matt Guthaus 550d5cc729 Fix path to config file in test 30 2018-11-09 16:33:08 -08:00
Matt Guthaus de61630962 Expand blocked pins to neighbor grid cells. 2018-11-09 14:25:10 -08:00
Matt Guthaus c5b408ae2d Add router output message 2018-11-09 11:10:40 -08:00
Matt Guthaus c01effc819 Adjust ptx positions in precharge to be under the bl rail 2018-11-09 10:26:15 -08:00
Matt Guthaus ac7229f8d3 Move vdd pin in precharge inside cell 2018-11-09 10:11:24 -08:00
Matt Guthaus cc619084c7 Clean up psingle_bank_test 2018-11-09 09:34:34 -08:00
Matt Guthaus 21f5fb0870 precharge bl is on metal2 only. simplify via position code. 2018-11-09 09:11:00 -08:00
Matt Guthaus 6aff552c0a Merge branch 'multiport_layout' of https://github.com/VLSIDA/PrivateRAM into multiport_layout 2018-11-09 08:53:27 -08:00
Matt Guthaus 8f3fa0e2f6 Fix blocked pin debug output. 2018-11-09 08:52:05 -08:00
Hunter Nichols 8957c556db Added sense amp enable delay calculation. 2018-11-08 23:54:18 -08:00
Hunter Nichols b8061d3a4e Added initial code for determining the logical effort delay of the wordline. 2018-11-08 23:54:18 -08:00
Jesse Cirimelli-Low d6c0247ff2 added area to datasheet 2018-11-08 21:30:17 -08:00
Jesse Cirimelli-Low 30bffdf1b4 Merge branch 'dev' into datasheet_gen 2018-11-08 19:26:00 -08:00
Matt Guthaus 9c8d5395ff Update leakage data for scn4m 2018-11-08 18:16:01 -08:00
Matt Guthaus 31eff6f24e Merge branch 'dev' into multiport_layout 2018-11-08 18:00:28 -08:00
Matt Guthaus 5d684b02e0 Leakage changed in ngspice test. 2018-11-08 18:00:09 -08:00
Matt Guthaus 71177d0b70 Fixed small bugs with new port index stuff and layout. 2018-11-08 17:40:22 -08:00
Matt Guthaus d03c9d5294 Fix write bl name list in replica bitline 2018-11-08 17:02:20 -08:00
Matt Guthaus fd5cd675ac Horizontal increments top down. 2018-11-08 17:01:57 -08:00
Matt Guthaus 18fbf30b46 Convert col decoder select routing to channel route. 2018-11-08 16:53:58 -08:00
Matt Guthaus e28978180f Vertical channel routes go from left right. Horizontal go bottom up. 2018-11-08 16:49:02 -08:00
Matt Guthaus ef2ed9a92c Simplify bl and br name lists. 2018-11-08 15:48:49 -08:00
Matt Guthaus 5d733154e9 Refactor bank to allow easier multiport. 2018-11-08 15:18:51 -08:00
Matt Guthaus 7b10e3bfec Convert port index lists to three simple lists. 2018-11-08 12:19:40 -08:00
Matt Guthaus b25650eb07 Netlist only mode for ngspice delay test 2018-11-08 12:19:06 -08:00
Matt Guthaus dd5b2a5b59 Fix missing fail when non-list item doesn't match. 2018-11-08 12:16:59 -08:00
Michael Timothy Grimes 7c3375fd4b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-08 09:59:52 -08:00
Matt Guthaus 929eae4a23 Document why sense amp is 8x isolation transistor 2018-11-07 16:09:50 -08:00
Matt Guthaus 5dfba21acc Change tx mux size back to 8. Document why it was chosen. 2018-11-07 16:03:48 -08:00
Matt Guthaus 3d2abc0873 Change default col mux size to 2. Add some comments. 2018-11-07 15:43:08 -08:00
Matt Guthaus ad7fe1be51 Clean up code formatting. 2018-11-07 14:52:03 -08:00
Matt Guthaus 4e232c49ad Update precharge cell for multiport. 
Comment out pbitcell tests.
Add bitcell_1rw_1r test.
Move bitcell horizontal routing to metal1.
Extend precharge height for stacking.
 2018-11-07 14:46:51 -08:00
Matt Guthaus 050035ae8d Add magic/netgen to example config 2018-11-07 13:54:00 -08:00
Matt Guthaus 2e5ae70391 Enable psram 1rw 2mux layout test. 2018-11-07 13:37:08 -08:00
Matt Guthaus f04e76a54f Allow multiple must-connect pins with the same label. 2018-11-07 13:05:13 -08:00
Matt Guthaus 8d753b5ac7 Primitive cells only keep the largest pin shape. 2018-11-07 11:58:31 -08:00
Matt Guthaus 1fe767343e Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup. 2018-11-07 11:31:44 -08:00
Jesse Cirimelli-Low 00dd6ddfd0 Merge branch 'dev' into datasheet_gen 2018-11-07 10:47:37 -08:00
Jesse Cirimelli-Low 781bd13cc1 Merge branch 'dev' into datasheet_gen 2018-11-07 10:08:45 -08:00
Matt Guthaus 485590052a Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing 2018-11-06 07:56:57 -08:00
Matt Guthaus 279fe4d103 Merge branch 'dev' into supply_routing 2018-11-06 07:56:29 -08:00
Matt Guthaus 86a8dca584 Merge branch 'dev' into supply_routing 2018-11-05 15:04:57 -08:00
Hunter Nichols ff169fcb2b Merged with dev, fixed config file conflict. 2018-11-05 14:58:52 -08:00
Hunter Nichols 4c26dede23 Unskipped functional tests and increases the number of ports on pbitcell functional tests. 2018-11-05 14:56:22 -08:00
Matt Guthaus 831e454b34 Remove redundant DRC run in magic. 2018-11-05 13:30:42 -08:00
Matt Guthaus 37b81c0af1 Remove options from example config files 2018-11-05 12:47:47 -08:00
Matt Guthaus 02bafb4757 Merge remote-tracking branch 'origin/dev' into supply_routing 2018-11-05 12:44:46 -08:00
Hunter Nichols 9744bc516a Merge branch 'dev' into multiport_characterization 2018-11-05 10:40:29 -08:00
Matt Guthaus ce94366a1d Skip all 4mux and 8mux tests until we solve teh simulation timing bug. 2018-11-05 09:50:44 -08:00
Michael Timothy Grimes 3c9821991b Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-11-05 08:56:19 -08:00
Matt Guthaus 38dab77bfc Add fixed seed to functional test during unit tests. Skip non-working tests after fixed seed. 2018-11-03 10:53:09 -07:00
Matt Guthaus 5d2df76ef5 Skip 4mux test 2018-11-03 10:16:22 -07:00
Matt Guthaus 5ecfa88d2a Pad the routing grid by a few tracks to add an extra rail 2018-11-02 17:35:35 -07:00
Matt Guthaus a3666d82ab Reduce verbosity of level 1 debug. 2018-11-02 17:30:28 -07:00
Hunter Nichols 7461f2b1bf Merged with dev. 2018-11-02 17:22:09 -07:00
Hunter Nichols f05865b307 Fixed drc issues with replica bitline test. 2018-11-02 17:16:41 -07:00
Matt Guthaus f8e761313a Merge branch 'dev' into supply_routing 2018-11-02 16:39:49 -07:00
Matt Guthaus 852bfbc031 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2018-11-02 16:34:36 -07:00
Matt Guthaus 6dd959b638 Fix error in 8mux test. Fix comment in all tests. 2018-11-02 16:34:26 -07:00
Matt Guthaus ad1d3a3c78 Use default grid costs again. 2018-11-02 16:04:56 -07:00
Matt Guthaus 3950a9feff Merge branch 'supply_routing' into dev 2018-11-02 15:31:29 -07:00
Matt Guthaus 74c3de2812 Remove diagonal routing bug. Cleanup. 2018-11-02 14:57:40 -07:00
Matt Guthaus ac203d987c Merge branch 'supply_routing' into dev 2018-11-02 11:50:46 -07:00
Matt Guthaus 866eaa8b02 Add debug message when routes are diagonal. 2018-11-02 11:50:28 -07:00
Matt Guthaus 4d30f214da Add expanded blockages for paths an enclosures to handle wide metal spacing rules. 2018-11-02 11:11:32 -07:00
Michael Timothy Grimes 6711630463 Altering the routing slightly in the column mux to give the gnd contacts a wider berth. This prevents drc errors when the bitlines are close to the edge of the cell. 2018-11-02 05:59:47 -07:00
Hunter Nichols 642dc8517c Added no mux functional test for 1rw+1r. Delay characterization also works for the custom cell as well. 2018-11-01 14:05:55 -07:00
Jesse Cirimelli-Low 3fa1d5522e added DRC/LVS error count to datasheet 2018-11-01 14:02:33 -07:00
Hunter Nichols b00fc040a3 Added replica 1rw+1r cell python modules. Also added drc/lvs checks in replica bitline, but test is failing due to pin error in freepdk45 and metal spacing error in scmos. 2018-11-01 12:29:49 -07:00
Matt Guthaus b24c8a42a1 Remove redundant pins in pin_group constructor. Clean up some code and comments. 2018-11-01 11:31:24 -07:00
Michael Timothy Grimes dc96d86082 Optimizations to pbitcell spacings 2018-11-01 07:58:20 -07:00
Matt Guthaus 2eedc703d1 Rename function in pin_group 2018-10-31 16:13:28 -07:00
Matt Guthaus c511d886bf Added new enclosure connector algorithm using edge sorting. 2018-10-31 15:35:39 -07:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Jesse Cirimelli-Low c3d7e24df9 fixed broken links when -o flag set 2018-10-31 09:34:36 -07:00
Matt Guthaus 673027ac8c Moved assert to check out_path earlier. 
Preserve temporary output directory with -d option.
 2018-10-31 09:37:47 -07:00
Hunter Nichols 9321f0461b Fixed error in control logic test. Added gds/sp for replica cell 1rw+1r. 2018-10-31 00:06:34 -07:00
Jesse Cirimelli-Low 5302fd205f fixed some final typos in datasheet 2018-10-30 23:03:05 -07:00
Jesse Cirimelli-Low 70ac2e8aa4 changed css to orange and black for Halloween; fixed CSb timing table in datasheet 2018-10-30 22:56:13 -07:00
Jesse Cirimelli-Low fe196c23a9 added FF timing information 2018-10-30 22:32:19 -07:00
Hunter Nichols e5dcf5d5b1 Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass. 2018-10-30 22:19:26 -07:00
Jesse Cirimelli-Low 905f6f8b43 added docstring and renamed some functions 2018-10-30 21:37:30 -07:00
Matt Guthaus fc45242ccb Allow contains to contain copy. Add connectors when pin doesn't overlap grids. 2018-10-30 17:41:29 -07:00
Matt Guthaus 7099ee76e9 Remove blocked grids from pins and secondary grids 2018-10-30 16:52:11 -07:00
Matt Guthaus 1344a8f7f1 Add remove adjacent feature for wide metal spacing 2018-10-30 12:24:13 -07:00
Matt Guthaus c4163d3401 Remove debug statements. 2018-10-29 13:50:56 -07:00
Matt Guthaus fa272be3bd Enumerate more enclosures. 2018-10-29 13:49:29 -07:00
Matt Guthaus cd87df8f76 Clean up enclosure code 2018-10-29 11:27:59 -07:00
Matt Guthaus f19bcace62 Merged in an old stash. 2018-10-29 11:18:12 -07:00
Matt Guthaus b7655eab10 Remove bug for combining pin with multiple other pins in a single iteration 2018-10-29 11:07:02 -07:00
Matt Guthaus bbffec863b Abandon connectors for now and opt for all enclosures 2018-10-29 10:59:22 -07:00
Matt Guthaus 6990773ea1 Add error check requiring non-zero area pin layouts. 2018-10-29 10:32:42 -07:00
Matt Guthaus 851aeae8c4 Add pins_enclosed function to pin_group 2018-10-29 10:28:57 -07:00
Jesse Cirimelli-Low 2da90c4b6a fixed double counting of characterization tuple permutations 2018-10-27 12:04:10 -07:00
Jesse Cirimelli-Low f1fb174b53 fixed bug where netlist_only still produced layout deliverables 2018-10-27 11:21:06 -07:00
Hunter Nichols 3bb8aa7e55 Fixed import errors with mux analytical delay model. 2018-10-26 17:37:25 -07:00
Matt Guthaus 0107e1c050 Reduce verbosity of utils 2018-10-26 13:02:31 -07:00
Matt Guthaus 7d74d34c53 Fix pin_layout contains bug 2018-10-26 10:40:43 -07:00
Matt Guthaus 4ce6b040fd Debugging missing enclosures 2018-10-26 09:25:10 -07:00
Jesse Cirimelli-Low fcfee649d5 moved css into a seperate file to organize and disambiguate docstrings from multiline strings 2018-10-26 07:57:54 -07:00
Hunter Nichols 98a00f985b Changed the analytical delay model to accept multiport options. Little substance to the values generated. 2018-10-26 00:08:13 -07:00
Hunter Nichols 6efe0f56c2 Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array. 2018-10-26 00:08:13 -07:00
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell. 2018-10-26 00:08:12 -07:00
Matt Guthaus 9e5d78cfc2 Fix bug in duplicate remove indices 2018-10-25 14:40:39 -07:00
Matt Guthaus 3407163cf1 Combine adjacent power supply pins finished 2018-10-25 14:25:52 -07:00
Matt Guthaus 0544d02ca2 Refactor router to have pin_groups for pins and router_tech file 2018-10-25 13:36:35 -07:00
Matt Guthaus 3f17679000 Merge remote-tracking branch 'origin' into supply_routing 2018-10-25 09:36:03 -07:00
Matt Guthaus 57fb847d50 Fix check for missing simulator type in characterizer 2018-10-25 09:08:56 -07:00
Matt Guthaus 3d8aeaa732 Run delay and setup/hold tests in netlist_only mode 2018-10-25 09:07:00 -07:00
Matt Guthaus 58de655aac Split functional tests 2018-10-25 08:56:23 -07:00
Michael Timothy Grimes 3202e1eb09 Altering comment code in simulation.py to match the needs of delay.py 2018-10-25 00:58:01 -07:00
Michael Timothy Grimes 40450ac0f5 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-25 00:36:46 -07:00
Michael Timothy Grimes ceab1a5daf Adding debug comments to stim file for functional test and cleaning up comment code in simulation.py. Adding multiple tests for different mux configurations to functional unit tests. 2018-10-25 00:11:00 -07:00
Matt Guthaus b1f3bd97e5 Enable all the 1bank tests. Mostly work in SCMOS. 2018-10-24 17:01:00 -07:00
Matt Guthaus 88f43cc754 Add the minimum pin enclosure that has DRC correct pin connections. 2018-10-24 16:41:33 -07:00
Matt Guthaus 94e5050513 Move overlap functions to pin_layout 2018-10-24 16:13:07 -07:00
Matt Guthaus dc73e8cb60 Odd bug that instances were not properly rotated. 2018-10-24 16:12:27 -07:00
Matt Guthaus 7e2bef624e Continue routing rails in same layer after a blockage 2018-10-24 12:32:27 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus cccde193d0 Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
Matt Guthaus 5f17525501 Added run-level option for write_control and enabled fast mode in functional tests 2018-10-24 09:32:44 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Matt Guthaus e90f9be6f5 Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Michael Timothy Grimes 2053a1ca4d Improved debug comments for functional test 2018-10-22 01:09:38 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 38a8c46034 Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 5276943ba2 Remove temp log file 2018-10-20 14:26:30 -07:00
Matt Guthaus 4c25bb09df Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
Matt Guthaus f5e68c5c32 Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias. 2018-10-20 12:54:12 -07:00
Matt Guthaus f9738253c6 Remove warning of track space and floor the space function. 2018-10-20 11:53:52 -07:00
Matt Guthaus a1f2a5befe Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 233a1425e4 Flatten bitcell array in netgen for now. See issue 52 2018-10-19 09:13:17 -07:00
jcirimel 74b806fa38
Merge pull request #54 from VLSIDA/datasheet_gen 
flask_table check fix
 2018-10-18 15:12:04 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Michael Timothy Grimes a06a0975db Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails 2018-10-15 13:58:40 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus a165446fa7 First implementation of multiple track spacing wide DRCs in routing grid. 2018-10-15 11:25:51 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Matt Guthaus 5e9fe65907 Remove banks from example configs 2018-10-12 10:23:34 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00
Jesse Cirimelli-Low 50cc8023a4 deleted output file left in previous commit 2018-10-11 16:04:43 -07:00
Jesse Cirimelli-Low 35e0ba6fc4 fixed merge error 2018-10-11 16:03:05 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low d142136735 rewrite of redirected print statements to file write 2018-10-11 12:09:50 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Matt Guthaus 297ea81060 Change RBL size to 50% of row size. 2018-10-11 10:39:24 -07:00
Matt Guthaus 1333329dd4 Merge branch 'multiport' into supply_routing 2018-10-11 10:37:10 -07:00
Matt Guthaus f7d1df6ca7 Fix trim spice with new names 2018-10-11 10:36:49 -07:00
Matt Guthaus e759c9350b Skip psram 1 bank 2018-10-11 10:17:50 -07:00
Matt Guthaus a094db9077 Merge branch 'multiport' into supply_routing 2018-10-11 09:56:38 -07:00
Matt Guthaus 823cb04b80 Fix metal4 rules in FreePDK45. Multiport still needs updating. 2018-10-11 09:56:15 -07:00
Matt Guthaus e22e658090 Converted all submodules to use _bit notation instead of [bit] 2018-10-11 09:53:08 -07:00
Matt Guthaus 3f2b7b837d Skip multibank for now too 2018-10-10 16:57:42 -07:00
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Hunter Nichols f30e54f33c Cleaned up indexing in variable that records cycle times. 2018-10-10 00:02:03 -07:00
Hunter Nichols 3ac2d29940 Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation 2018-10-09 17:44:28 -07:00
Hunter Nichols a3bec5518c Put worst case test under the hierarchy of a delay test. Added option for pex option to worst case test. 2018-10-09 00:36:14 -07:00
Hunter Nichols fd806077d2 Added class and test for testing the delay of several bitcells. 2018-10-08 15:50:52 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Jesse Cirimelli-Low 49268b025f fixed /tmp/ typo 2018-10-06 21:17:26 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 83fd2c0512 Fix openram_temp directory 2018-10-06 08:08:01 -07:00
Matt Guthaus 94ab69ea16 Supply router working, perhaps not efficiently though. 2018-10-05 15:57:34 -07:00
Matt Guthaus eb2304944b Fix .magicrc file name 2018-10-05 08:48:25 -07:00
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets. 2018-10-05 08:39:28 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 19114fe47f Add commented extraction when running DRC only 2018-10-05 08:18:53 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Matt Guthaus c3cd76048b Removed prints. Fixed offset for single track enclosure. 2018-10-04 14:44:25 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols bb79d9a62d Added regex pattern matching to trim_spice to handle multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes cf4b216888 Correcting functional inheritance from simulation. 2018-10-04 13:55:59 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00
Michael Timothy Grimes 648e57d195 Altering bank select for port specific use. Altering bank select test to test different port types. Altering bank for control signal changes. 2018-09-26 14:53:55 -07:00
Michael Timothy Grimes f1560375fc Altering control logic for read ports and write ports, by including only read or write specific circuitry. Altering replica bitline layout to support multiport 2018-09-25 20:00:25 -07:00
Matt Guthaus a7246f5e7f Rename omits 0 size ports 2018-09-24 13:44:31 -07:00
Matt Guthaus 9b0142d6b9 Comment debug for possible performance issue 2018-09-24 11:44:32 -07:00
Matt Guthaus a3f13d6eab Remove banks from test configs 2018-09-24 11:41:51 -07:00
Matt Guthaus 2df9b79b28 Remove scn3me lib files. Remove bank references. 2018-09-24 11:28:43 -07:00
Matt Guthaus 7432192e5e Small change to test webhook 2018-09-24 09:11:44 -07:00
Matt Guthaus 922e3f4c13 Small change to test webhook 2018-09-21 15:05:46 -07:00
Matt Guthaus ade12c9dc2 Small change to test webhook 2018-09-21 15:03:16 -07:00
Matt Guthaus e1864a7a1e Small change to test webhook 2018-09-21 15:02:16 -07:00
Matt Guthaus 2b3b4bbee6 Small change to test webhook 2018-09-21 15:01:07 -07:00
Michael Timothy Grimes 934959952b Corrections to functional test that adds multiple cs_b signals per port 2018-09-21 09:59:44 -07:00
Matt Guthaus 87502374c5 DRC clean supply grid routing on control logic. 2018-09-20 16:00:13 -07:00
Michael Timothy Grimes 2641841e4c Making correction to replica bitline netlist for multiport 2018-09-20 15:21:22 -07:00
Michael Timothy Grimes 938ded3dd6 Adding functional test to characterizer and unit tests in both single and multiport 2018-09-20 15:04:59 -07:00
Michael Timothy Grimes fc5f163828 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-18 18:56:15 -07:00
Matt Guthaus fd9ffe30d6 Add layer width options to route object 
Modify router to use track-width routes.
 2018-09-18 15:12:53 -07:00
Matt Guthaus 8d2804b9cb Supply router working except: 
Off grid pins. Some pins do now span enough of the routing track and must be patched.
  Route track width. Instead of minimum width route, it should be the track width.
 2018-09-18 12:57:39 -07:00
Matt Guthaus bfc8428df7 Convert router tests to scn4m_subm 2018-09-17 13:30:30 -07:00
Matt Guthaus 60cceab50a Merge branch 'dev' into supply_routing 2018-09-17 11:34:31 -07:00
Matt Guthaus a58b1906ad Convert unit tests to scn4m_subm 
Also, fixed isdiff for python3.
 2018-09-17 11:13:46 -07:00
Michael Timothy Grimes 43f5316eed Correcting format of replica_pbitcell. 2018-09-13 18:51:52 -07:00
Michael Timothy Grimes 9acc8a9532 Altering multiport checks across several unit tests. 2018-09-13 18:49:20 -07:00
Michael Timothy Grimes 332976dd73 s_en will be shared amongst the sense amps of different ports, so I'm removing the distinct s_en signals from several modules. 2018-09-13 18:46:43 -07:00
Michael Timothy Grimes 5fd484ee5a Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode. 2018-09-13 16:53:24 -07:00
Matt Guthaus e591176211 Change default to scn4m 2018-09-13 15:26:03 -07:00
Matt Guthaus 93ae7ebd00 Specify DRC,LVS,PEX tool for scn4m 2018-09-13 15:18:30 -07:00
Matt Guthaus 571dca5d5f Hard code flatten commands for the unique id precharge array 2018-09-13 15:15:41 -07:00
Matt Guthaus 4d328c5768 Fix hspice setuphold golden results 2018-09-13 14:41:15 -07:00
Matt Guthaus f4389bdd8f Add extra track spacings in some routes. 2018-09-13 14:12:24 -07:00
Matt Guthaus 63d0523228 Added scn4m_subm. 
Added scn4m_subm files (instead of scn4me_subm).
Fixed missing cifoutput/cifinput in magic tech file and gds files.
Fixed incorrect M3/via3/M4 design rules.
 2018-09-13 12:53:35 -07:00
Matt Guthaus 3539887ee4 Updating ms_flop removal. 
Updated characterizer for dff.
Added new setup/hold results for dff instead of ms_flop.
Removed ms_flop references in sram-base.
Fixed syntax errors in SCN3ME tech file.
 2018-09-13 11:40:24 -07:00
Matt Guthaus 66cbe0966c Removed old ms_flop unit test 2018-09-13 11:15:33 -07:00