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Remove extraneous m2m3 via that causes DRC

This commit is contained in:
Matt Guthaus 2018-12-06 12:45:45 -08:00
parent b5a7274316
commit 6f1af4d0c9
1 changed files with 2 additions and 3 deletions
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5
compiler/sram_1bank.py
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@ -203,9 +203,8 @@ class sram_1bank(sram_base):
offset=clk_steiner_pos,
rotate=90)
# Note, the via to the control logic is taken care of when we route
# the control logic to the bank
self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos, control_clk_buf_pos])
# Note, the via to the control logic is taken care of above
self.add_wire(("metal3","via2","metal2"),[row_addr_clk_pos, mid1_pos, clk_steiner_pos])
if self.col_addr_dff:
dff_clk_pin = self.col_addr_dff_insts[port].get_pin("clk")