mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
This commit is contained in:
Matt Guthaus
commit
be9f81768d
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|
@ -31,7 +31,6 @@ The OpenRAM compiler has very few dependencies:
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+ [Ngspice] 26 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later)
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+ Python 3.5 or higher
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+ Python numpy (pip3 install numpy to install)
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+ flask_table (pip3 install flask to install)
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If you want to perform DRC and LVS, you will need either:
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+ Calibre (for [FreePDK45])
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@ -1,23 +0,0 @@
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from flask_table import *
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class characterization_corners(Table):
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"""
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Set up characterization corners table columns and title information
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"""
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corner_name = Col('Corner Name')
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process = Col('Process')
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power_supply = Col('Power Supply')
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temperature = Col('Temperature')
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library_name_suffix = Col('Library Name Suffix')
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class characterization_corners_item(object):
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"""
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Defines the contents of a charcaterization corner table row
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"""
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def __init__(self, corner_name, process, power_supply, temperature, library_name_suffix):
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self.corner_name = corner_name
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self.process = process
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self.power_supply = power_supply
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self.temperature = temperature
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self.library_name_suffix = library_name_suffix
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@ -1,9 +1,4 @@
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from flask_table import *
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from operating_conditions import *
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from characterization_corners import *
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from deliverables import *
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from timing_and_current_data import *
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from in_out import *
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from table_gen import *
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import os
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import csv
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import base64
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@ -14,11 +9,6 @@ class datasheet():
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Defines the layout,but not the data, of the html datasheet
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"""
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def __init__(self,identifier):
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self.io = []
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self.corners = []
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self.timing = []
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self.operating = []
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self.dlv = []
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self.name = identifier
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self.html = ""
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@ -58,24 +48,29 @@ class datasheet():
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ self.name + '.html' + '</p>'
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Compiled at: '+ self.time + '</p>'
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC: ' + str(self.DRC) + '</p>'
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS: ' + str(self.LVS) + '</p>'
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'DRC errors: ' + str(self.DRC) + '</p>'
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self.html +='<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'LVS errors: ' + str(self.LVS) + '</p>'
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self.html += '<p style="font-size: 18px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">'+ 'Git commit id: ' + str(self.git_id) + '</p>'
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self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration (DEBUG)</p>'
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self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">")
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self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Ports and Configuration</p>'
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# self.html += in_out(self.io,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">")
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self.html += self.io_table.to_html()
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self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Operating Conditions</p>'
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self.html += operating_conditions(self.operating,table_id='data').__html__()
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# self.html += operating_conditions(self.operating,table_id='data').__html__()
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self.html += self.operating_table.to_html()
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Timing and Current Data</p>'
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self.html += timing_and_current_data(self.timing,table_id='data').__html__()
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# self.html += timing_and_current_data(self.timing,table_id='data').__html__()
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self.html += self.timing_table.to_html()
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self.html += '<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Characterization Corners</p>'
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self.html += characterization_corners(self.corners,table_id='data').__html__()
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# self.html += characterization_corners(self.corners,table_id='data').__html__()
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self.html += self.corners_table.to_html()
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self.html +='<p style="font-size: 26px;font-family: Trebuchet MS, Arial, Helvetica, sans-serif;">Deliverables</p>'
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self.html += deliverables(self.dlv,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">")
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# self.html += deliverables(self.dlv,table_id='data').__html__().replace('<','<').replace('"','"').replace('>',">")
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self.html += self.dlv_table.to_html()
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@ -1,34 +1,21 @@
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#!/usr/bin/env python3
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"""
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This is a script to load data from the characterization and layout processes into
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a web friendly html datasheet. This script requres the python-flask and flask-table
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packages to be installed.
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a web friendly html datasheet.
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"""
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#TODO:
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#locate all port elements in .lib
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#Locate all timing elements in .lib
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#include log file
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#Diagram generation
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#Improve css
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import debug
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from globals import OPTS
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if OPTS.datasheet_gen:
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import flask_table
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import os, math
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import optparse
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import csv
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from deliverables import *
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from operating_conditions import *
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from timing_and_current_data import *
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from characterization_corners import *
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from datasheet import *
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from in_out import *
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else:
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debug.warning("Python library flask_table not found. Skipping html datasheet generation. This can be installed with pip install flask-table.")
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#make sure appropriate python libraries are installed
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import os, math
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import optparse
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import csv
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from datasheet import *
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from table_gen import *
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def process_name(corner):
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"""
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@ -119,69 +106,70 @@ def parse_characterizer_csv(sram,f,pages):
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found = 1
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#if the .lib information is for an existing datasheet compare timing data
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for item in sheet.operating:
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for item in sheet.operating_table.rows:
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#check if the new corner data is worse than the previous worse corner data
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if item.parameter == 'Operating Temperature':
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if float(TEMP) > float(item.max):
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item.typ = item.max
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item.max = TEMP
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if float(TEMP) < float(item.min):
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item.typ = item.min
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item.min = TEMP
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if item[0] == 'Operating Temperature':
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if float(TEMP) > float(item[3]):
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item[2] = item[3]
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item[3] = TEMP
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if float(TEMP) < float(item[1]):
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item[2] = item[1]
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item[1] = TEMP
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if item.parameter == 'Power supply (VDD) range':
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if float(VOLT) > float(item.max):
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item.typ = item.max
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item.max = VOLT
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if float(VOLT) < float(item.min):
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item.typ = item.min
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item.min = VOLT
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if item[0] == 'Power supply (VDD) range':
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if float(VOLT) > float(item[3]):
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item[2] = item[3]
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item[3] = VOLT
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if float(VOLT) < float(item[1]):
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item[2] = item[1]
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item[1] = VOLT
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if item.parameter == 'Operating Frequncy (F)':
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if item[0] == 'Operating Frequncy (F)':
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try:
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if float(math.floor(1000/float(MIN_PERIOD)) < float(item.max)):
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item.max = str(math.floor(1000/float(MIN_PERIOD)))
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if float(math.floor(1000/float(MIN_PERIOD)) < float(item[3])):
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item[3] = str(math.floor(1000/float(MIN_PERIOD)))
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except Exception:
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pass
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while(True):
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if(row[col].startswith('DIN')):
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start = col
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for item in sheet.timing:
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if item.parameter.startswith(row[col]):
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for item in sheet.timing_table.rows:
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if item[0].startswith(row[col]):
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if item.parameter.endswith('setup rising'):
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if float(row[col+1]) < float(item.min):
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item.min = row[col+1]
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if float(row[col+2]) > float(item.max):
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item.max = row[col+2]
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if item[0].endswith('setup rising'):
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if float(row[col+1]) < float(item[1]):
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item[1] = row[col+1]
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if float(row[col+2]) > float(item[2]):
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item[2] = row[col+2]
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col += 2
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elif item.parameter.endswith('setup falling'):
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if float(row[col+1]) < float(item.min):
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item.min = row[col+1]
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if float(row[col+2]) > float(item.max):
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item.max = row[col+2]
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elif item[0].endswith('setup falling'):
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if float(row[col+1]) < float(item[1]):
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item[1] = row[col+1]
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if float(row[col+2]) > float(item[2]):
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item[2] = row[col+2]
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col += 2
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elif item.parameter.endswith('hold rising'):
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if float(row[col+1]) < float(item.min):
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item.min = row[col+1]
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if float(row[col+2]) > float(item.max):
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item.max = row[col+2]
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elif item[0].endswith('hold rising'):
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if float(row[col+1]) < float(item[1]):
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item[1] = row[col+1]
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if float(row[col+2]) > float(item[2]):
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item[2] = row[col+2]
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col += 2
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|
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elif item.parameter.endswith('hold falling'):
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if float(row[col+1]) < float(item.min):
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item.min = row[col+1]
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if float(row[col+2]) > float(item.max):
|
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item.max = row[col+2]
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elif item[0].endswith('hold falling'):
|
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if float(row[col+1]) < float(item[1]):
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item[1] = row[col+1]
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if float(row[col+2]) > float(item[2]):
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item[2] = row[col+2]
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|
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col += 2
|
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|
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|
|
@ -189,38 +177,38 @@ def parse_characterizer_csv(sram,f,pages):
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|
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elif(row[col].startswith('DOUT')):
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start = col
|
||||
for item in sheet.timing:
|
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if item.parameter.startswith(row[col]):
|
||||
for item in sheet.timing_table.rows:
|
||||
if item[0].startswith(row[col]):
|
||||
|
||||
if item.parameter.endswith('cell rise'):
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if float(row[col+1]) < float(item.min):
|
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item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
if item[0].endswith('cell rise'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('cell fall'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('cell fall'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('rise transition'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('rise transition'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('fall transition'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('fall transition'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
|
|
@ -228,38 +216,38 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
|
||||
elif(row[col].startswith('CSb')):
|
||||
start = col
|
||||
for item in sheet.timing:
|
||||
if item.parameter.startswith(row[col]):
|
||||
for item in sheet.timing_table.rows:
|
||||
if item[0].startswith(row[col]):
|
||||
|
||||
if item.parameter.endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
if item[0].endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
|
|
@ -268,38 +256,38 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
|
||||
elif(row[col].startswith('WEb')):
|
||||
start = col
|
||||
for item in sheet.timing:
|
||||
if item.parameter.startswith(row[col]):
|
||||
for item in sheet.timing_table.rows:
|
||||
if item[0].startswith(row[col]):
|
||||
|
||||
if item.parameter.endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
if item[0].endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
|
|
@ -308,38 +296,38 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
|
||||
elif(row[col].startswith('ADDR')):
|
||||
start = col
|
||||
for item in sheet.timing:
|
||||
if item.parameter.startswith(row[col]):
|
||||
for item in sheet.timing_table.rows:
|
||||
if item[0].startswith(row[col]):
|
||||
|
||||
if item.parameter.endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
if item[0].endswith('setup rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('setup falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold rising'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
elif item.parameter.endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item.min):
|
||||
item.min = row[col+1]
|
||||
if float(row[col+2]) > float(item.max):
|
||||
item.max = row[col+2]
|
||||
elif item[0].endswith('hold falling'):
|
||||
if float(row[col+1]) < float(item[1]):
|
||||
item[1] = row[col+1]
|
||||
if float(row[col+2]) > float(item[2]):
|
||||
item[2] = row[col+2]
|
||||
|
||||
col += 2
|
||||
|
||||
|
|
@ -351,9 +339,8 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
break
|
||||
|
||||
|
||||
#regardless of if there is already a corner for the current sram, append the new corner to the datasheet
|
||||
new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
|
||||
new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
|
||||
new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
|
||||
new_sheet.dlv_table.add_row(['.lib','Synthesis models','<a href="file://{0}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
|
||||
|
||||
if found == 0:
|
||||
|
||||
|
|
@ -367,127 +354,157 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
new_sheet.LVS = LVS
|
||||
new_sheet.description = [NAME, NUM_WORDS, NUM_BANKS, NUM_RW_PORTS, NUM_W_PORTS, NUM_R_PORTS, TECH_NAME, WORD_SIZE, ORIGIN_ID, DATETIME]
|
||||
|
||||
new_sheet.corners_table = table_gen("corners")
|
||||
new_sheet.corners_table.add_row(['Corner Name','Process','Power Supply','Temperature','Library Name Suffix'])
|
||||
new_sheet.corners_table.add_row([PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')])
|
||||
new_sheet.operating_table = table_gen("operating_table")
|
||||
new_sheet.operating_table.add_row(['Parameter','Min','Typ','Max','Units'])
|
||||
new_sheet.operating_table.add_row(['Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'])
|
||||
new_sheet.operating_table.add_row(['Operating Temperature',TEMP,TEMP,TEMP,'Celsius'])
|
||||
|
||||
new_sheet.corners.append(characterization_corners_item(PROC,process_name(PROC),VOLT,TEMP,LIB_NAME.replace(OUT_DIR,'').replace(NAME,'')))
|
||||
|
||||
new_sheet.operating.append(operating_conditions_item('Power supply (VDD) range',VOLT,VOLT,VOLT,'Volts'))
|
||||
new_sheet.operating.append(operating_conditions_item('Operating Temperature',TEMP,TEMP,TEMP,'Celsius'))
|
||||
try:
|
||||
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'))
|
||||
new_sheet.operating_table.add_row(['Operating Frequency (F)','','',str(math.floor(1000/float(MIN_PERIOD))),'MHz'])
|
||||
except Exception:
|
||||
new_sheet.operating.append(operating_conditions_item('Operating Frequency (F)','','',"not available in netlist only",'MHz')) #failed to provide non-zero MIN_PERIOD
|
||||
|
||||
|
||||
new_sheet.operating_table.add_row(['Operating Frequency (F)','','',"not available in netlist only",'MHz']) #failed to provide non-zero MIN_PERIOD
|
||||
new_sheet.timing_table = table_gen("timing")
|
||||
new_sheet.timing_table.add_row(['Parameter','Min','Max','Units'])
|
||||
while(True):
|
||||
if(row[col].startswith('DIN')):
|
||||
start = col
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
col +=1
|
||||
|
||||
|
||||
elif(row[col].startswith('DOUT')):
|
||||
start = col
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} cell rise'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} cell fall'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} rise transition'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} fall transition'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
col +=1
|
||||
|
||||
elif(row[col].startswith('CSb')):
|
||||
start = col
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
col +=1
|
||||
|
||||
elif(row[col].startswith('WEb')):
|
||||
start = col
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
col +=1
|
||||
|
||||
elif(row[col].startswith('ADDR')):
|
||||
start = col
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
|
||||
new_sheet.timing_table.add_row(['{0} setup falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold rising'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
new_sheet.timing.append(timing_and_current_data_item('{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'))
|
||||
new_sheet.timing_table.add_row(['{0} hold falling'.format(row[start]),row[col+1],row[col+2],'ns'])
|
||||
|
||||
col += 2
|
||||
|
||||
col +=1
|
||||
|
||||
else:
|
||||
break
|
||||
|
||||
|
||||
|
||||
|
||||
new_sheet.dlv_table = table_gen("dlv")
|
||||
new_sheet.dlv_table.add_row(['Type','Description','Link'])
|
||||
|
||||
new_sheet.io_table = table_gen("io")
|
||||
new_sheet.io_table.add_row(['Type', 'Value'])
|
||||
|
||||
if not OPTS.netlist_only:
|
||||
#physical layout files should not be generated in netlist only mode
|
||||
new_sheet.dlv.append(deliverables_item('.gds','GDSII layout views','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'gds')))
|
||||
new_sheet.dlv.append(deliverables_item('.lef','LEF files','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'lef')))
|
||||
|
||||
|
||||
new_sheet.dlv.append(deliverables_item('.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')))
|
||||
new_sheet.dlv.append(deliverables_item('.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')))
|
||||
new_sheet.dlv.append(deliverables_item('.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')))
|
||||
new_sheet.dlv.append(deliverables_item('.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))))
|
||||
new_sheet.dlv.append(deliverables_item('.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')))
|
||||
|
||||
|
||||
|
||||
#debug table for multiport information
|
||||
new_sheet.io.append(in_out_item('WORD_SIZE',WORD_SIZE))
|
||||
new_sheet.io.append(in_out_item('NUM_WORDS',NUM_WORDS))
|
||||
new_sheet.io.append(in_out_item('NUM_BANKS',NUM_BANKS))
|
||||
new_sheet.io.append(in_out_item('NUM_RW_PORTS',NUM_RW_PORTS))
|
||||
new_sheet.io.append(in_out_item('NUM_R_PORTS',NUM_R_PORTS))
|
||||
new_sheet.io.append(in_out_item('NUM_W_PORTS',NUM_W_PORTS))
|
||||
new_sheet.io.append(in_out_item('Area',sram.width * sram.height))
|
||||
|
||||
new_sheet.dlv_table.add_row(['.gds','GDSII layout views','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'gds')])
|
||||
new_sheet.dlv_table.add_row(['.lef','LEF files','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'lef')])
|
||||
|
||||
|
||||
new_sheet.dlv_table.add_row(['.sp','SPICE netlists','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'sp')])
|
||||
new_sheet.dlv_table.add_row(['.v','Verilog simulation models','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'v')])
|
||||
new_sheet.dlv_table.add_row(['.html','This datasheet','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'html')])
|
||||
new_sheet.dlv_table.add_row(['.lib','Synthesis models','<a href="{1}">{1}</a>'.format(LIB_NAME,LIB_NAME.replace(OUT_DIR,''))])
|
||||
new_sheet.dlv_table.add_row(['.py','OpenRAM configuration file','<a href="{0}.{1}">{0}.{1}</a>'.format(OPTS.output_name,'py')])
|
||||
|
||||
new_sheet.io_table.add_row(['WORD_SIZE',WORD_SIZE])
|
||||
new_sheet.io_table.add_row(['NUM_WORDS',NUM_WORDS])
|
||||
new_sheet.io_table.add_row(['NUM_BANKS',NUM_BANKS])
|
||||
new_sheet.io_table.add_row(['NUM_RW_PORTS',NUM_RW_PORTS])
|
||||
new_sheet.io_table.add_row(['NUM_R_PORTS',NUM_R_PORTS])
|
||||
new_sheet.io_table.add_row(['NUM_W_PORTS',NUM_W_PORTS])
|
||||
new_sheet.io_table.add_row(['Area',sram.width * sram.height])
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -496,18 +513,18 @@ def parse_characterizer_csv(sram,f,pages):
|
|||
class datasheet_gen():
|
||||
def datasheet_write(sram,name):
|
||||
|
||||
if OPTS.datasheet_gen:
|
||||
in_dir = OPTS.openram_temp
|
||||
|
||||
if not (os.path.isdir(in_dir)):
|
||||
os.mkdir(in_dir)
|
||||
|
||||
in_dir = OPTS.openram_temp
|
||||
|
||||
if not (os.path.isdir(in_dir)):
|
||||
os.mkdir(in_dir)
|
||||
|
||||
|
||||
datasheets = []
|
||||
parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets)
|
||||
datasheets = []
|
||||
parse_characterizer_csv(sram, in_dir + "/datasheet.info", datasheets)
|
||||
|
||||
|
||||
for sheets in datasheets:
|
||||
with open(name, 'w+') as f:
|
||||
sheets.generate_html()
|
||||
f.write(sheets.html)
|
||||
for sheets in datasheets:
|
||||
with open(name, 'w+') as f:
|
||||
sheets.generate_html()
|
||||
f.write(sheets.html)
|
||||
|
|
|
|||
|
|
@ -1,19 +0,0 @@
|
|||
from flask_table import *
|
||||
|
||||
class deliverables(Table):
|
||||
"""
|
||||
Set up delivarables table columns and title information
|
||||
"""
|
||||
typ = Col('Type')
|
||||
description = Col('Description')
|
||||
link = Col('Link')
|
||||
|
||||
|
||||
class deliverables_item(object):
|
||||
"""
|
||||
Define deliverables table row elemenent information
|
||||
"""
|
||||
def __init__(self, typ, description,link):
|
||||
self.typ = typ
|
||||
self.description = description
|
||||
self.link = link
|
||||
|
|
@ -1,17 +0,0 @@
|
|||
from flask_table import *
|
||||
|
||||
class in_out(Table):
|
||||
"""
|
||||
Set up I/O table columns and title information for multiport debugging
|
||||
"""
|
||||
typ = Col('Type')
|
||||
description = Col('Description')
|
||||
|
||||
|
||||
class in_out_item(object):
|
||||
"""
|
||||
Define table row element for I/O table
|
||||
"""
|
||||
def __init__(self, typ, description):
|
||||
self.typ = typ
|
||||
self.description = description
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
from flask_table import *
|
||||
|
||||
class operating_conditions(Table):
|
||||
"""
|
||||
Set up operating conditions columns and title information
|
||||
"""
|
||||
parameter = Col('Parameter')
|
||||
min = Col('Min')
|
||||
typ = Col('Typ')
|
||||
max = Col('Max')
|
||||
units = Col('Units')
|
||||
|
||||
class operating_conditions_item(object):
|
||||
"""
|
||||
Define operating conditions table row element
|
||||
"""
|
||||
def __init__(self, parameter, min, typ, max, units):
|
||||
self.parameter = parameter
|
||||
self.min = min
|
||||
self.typ = typ
|
||||
self.max = max
|
||||
self.units = units
|
||||
|
||||
|
|
@ -1,24 +0,0 @@
|
|||
import os
|
||||
import jinja2
|
||||
from flask import Flask, render_template
|
||||
from filelist import *
|
||||
|
||||
|
||||
filedir = './files'
|
||||
file_data = './filelist.info'
|
||||
|
||||
|
||||
app = Flask('server_scripts')
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
|
||||
files = filelist()
|
||||
|
||||
files.update_filelist(filedir,file_data)
|
||||
|
||||
f = open('./index.html','w')
|
||||
with app.app_context():
|
||||
f.write(render_template('index.html', filedir = filedir , os = os))
|
||||
|
||||
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
import csv
|
||||
|
||||
class version_data:
|
||||
|
||||
|
|
@ -1,13 +0,0 @@
|
|||
./files/test_files/sram_2_16_scn4m_subm.py
|
||||
./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib
|
||||
./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib
|
||||
./files/test_files/sram_2_16_scn4m_subm.sp
|
||||
./files/test_files/sram_2_16_scn4m_subm.v
|
||||
./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib
|
||||
./files/test_files/sram_2_16_scn4m_subm.gds
|
||||
./files/test_files/sram_2_16_scn4m_subm.html
|
||||
./files/test_files/sram_2_16_scn4m_subm.lef
|
||||
./files/test_files/testfolder/file2
|
||||
./files/test_files/testfolder/file1
|
||||
./files/test_files/testfolder2/file4
|
||||
./files/test_files/testfolder2/file3
|
||||
|
|
@ -1,16 +0,0 @@
|
|||
import os
|
||||
from deliverable import *
|
||||
class filelist:
|
||||
|
||||
|
||||
def __init__(self):
|
||||
self.list = []
|
||||
|
||||
def update_filelist(self,path,outdir):
|
||||
out_file = open(outdir,'w')
|
||||
for root, dirs, files in os.walk(path):
|
||||
for file in files:
|
||||
self.list.append(root + '/' + file)
|
||||
out_file.write('{}/{}\n'.format(root,file))
|
||||
#print('{}/{}'.format(root,file))
|
||||
|
||||
Binary file not shown.
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -1,18 +0,0 @@
|
|||
word_size = 2
|
||||
num_words = 16
|
||||
|
||||
tech_name = "scn4m_subm"
|
||||
process_corners = ["TT"]
|
||||
supply_voltages = [ 5.0 ]
|
||||
temperatures = [ 25 ]
|
||||
|
||||
output_path = "temp"
|
||||
output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
|
||||
|
||||
#Setting for multiport
|
||||
netlist_only = True
|
||||
bitcell = "pbitcell"
|
||||
replica_bitcell="replica_pbitcell"
|
||||
num_rw_ports = 1
|
||||
num_r_ports = 0
|
||||
num_w_ports = 0
|
||||
|
|
@ -1,559 +0,0 @@
|
|||
**************************************************
|
||||
* OpenRAM generated memory.
|
||||
* Words: 16
|
||||
* Data bits: 2
|
||||
* Banks: 1
|
||||
* Column mux: 1:1
|
||||
**************************************************
|
||||
*********************** "dff" ******************************
|
||||
* Positive edge-triggered FF
|
||||
.SUBCKT dff D Q clk vdd gnd
|
||||
|
||||
* SPICE3 file created from dff.ext - technology: scmos
|
||||
|
||||
M1000 vdd clk a_24_24# vdd p w=8u l=0.4u
|
||||
M1001 a_84_296# D vdd vdd p w=4u l=0.4u
|
||||
M1002 a_104_24# clk a_84_296# vdd p w=4u l=0.4u
|
||||
M1003 a_140_296# a_24_24# a_104_24# vdd p w=4u l=0.4u
|
||||
M1004 vdd a_152_16# a_140_296# vdd p w=4u l=0.4u
|
||||
M1005 a_152_16# a_104_24# vdd vdd p w=4u l=0.4u
|
||||
M1006 a_260_296# a_152_16# vdd vdd p w=4u l=0.4u
|
||||
M1007 a_280_24# a_24_24# a_260_296# vdd p w=4u l=0.4u
|
||||
M1008 a_320_336# clk a_280_24# vdd p w=2u l=0.4u
|
||||
M1009 vdd Q a_320_336# vdd p w=2u l=0.4u
|
||||
M1010 gnd clk a_24_24# gnd n w=4u l=0.4u
|
||||
M1011 Q a_280_24# vdd vdd p w=8u l=0.4u
|
||||
M1012 a_84_24# D gnd gnd n w=2u l=0.4u
|
||||
M1013 a_104_24# a_24_24# a_84_24# gnd n w=2u l=0.4u
|
||||
M1014 a_140_24# clk a_104_24# gnd n w=2u l=0.4u
|
||||
M1015 gnd a_152_16# a_140_24# gnd n w=2u l=0.4u
|
||||
M1016 a_152_16# a_104_24# gnd gnd n w=2u l=0.4u
|
||||
M1017 a_260_24# a_152_16# gnd gnd n w=2u l=0.4u
|
||||
M1018 a_280_24# clk a_260_24# gnd n w=2u l=0.4u
|
||||
M1019 a_320_24# a_24_24# a_280_24# gnd n w=2u l=0.4u
|
||||
M1020 gnd Q a_320_24# gnd n w=2u l=0.4u
|
||||
M1021 Q a_280_24# gnd gnd n w=4u l=0.4u
|
||||
|
||||
.ENDS
|
||||
|
||||
.SUBCKT row_addr_dff din_0 din_1 din_2 din_3 dout_0 dout_1 dout_2 dout_3 clk vdd gnd
|
||||
Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
|
||||
Xdff_r1_c0 din_1 dout_1 clk vdd gnd dff
|
||||
Xdff_r2_c0 din_2 dout_2 clk vdd gnd dff
|
||||
Xdff_r3_c0 din_3 dout_3 clk vdd gnd dff
|
||||
.ENDS row_addr_dff
|
||||
|
||||
.SUBCKT data_dff din_0 din_1 dout_0 dout_1 clk vdd gnd
|
||||
Xdff_r0_c0 din_0 dout_0 clk vdd gnd dff
|
||||
Xdff_r0_c1 din_1 dout_1 clk vdd gnd dff
|
||||
.ENDS data_dff
|
||||
|
||||
* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
|
||||
* ptx M{0} {1} p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
|
||||
|
||||
* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
|
||||
* ptx M{0} {1} n m=1 w=1.2000000000000002u l=0.4u pd=3.20u ps=3.20u as=1.20p ad=1.20p
|
||||
|
||||
.SUBCKT pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
|
||||
Minverter_nmos_left Q Q_bar gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Minverter_nmos_right gnd Q Q_bar gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Minverter_pmos_left Q Q_bar vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
|
||||
Minverter_pmos_right vdd Q Q_bar vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
|
||||
Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
Mreadwrite_nmos_right0 Q_bar wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pbitcell_1RW_0W_0R
|
||||
|
||||
.SUBCKT bitcell_array_16x2_1 bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd
|
||||
Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r8_c0 bl0_0 br0_0 wl0_8 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r9_c0 bl0_0 br0_0 wl0_9 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r10_c0 bl0_0 br0_0 wl0_10 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r11_c0 bl0_0 br0_0 wl0_11 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r12_c0 bl0_0 br0_0 wl0_12 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r13_c0 bl0_0 br0_0 wl0_13 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r14_c0 bl0_0 br0_0 wl0_14 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r15_c0 bl0_0 br0_0 wl0_15 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r0_c1 bl0_1 br0_1 wl0_0 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r1_c1 bl0_1 br0_1 wl0_1 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r2_c1 bl0_1 br0_1 wl0_2 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r3_c1 bl0_1 br0_1 wl0_3 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r4_c1 bl0_1 br0_1 wl0_4 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r5_c1 bl0_1 br0_1 wl0_5 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r6_c1 bl0_1 br0_1 wl0_6 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r7_c1 bl0_1 br0_1 wl0_7 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r8_c1 bl0_1 br0_1 wl0_8 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r9_c1 bl0_1 br0_1 wl0_9 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r10_c1 bl0_1 br0_1 wl0_10 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r11_c1 bl0_1 br0_1 wl0_11 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r12_c1 bl0_1 br0_1 wl0_12 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r13_c1 bl0_1 br0_1 wl0_13 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r14_c1 bl0_1 br0_1 wl0_14 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r15_c1 bl0_1 br0_1 wl0_15 vdd gnd pbitcell_1RW_0W_0R
|
||||
.ENDS bitcell_array_16x2_1
|
||||
|
||||
* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
|
||||
.SUBCKT precharge_1 bl br en_bar vdd
|
||||
Mlower_pmos bl en_bar br vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mupper_pmos1 bl en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mupper_pmos2 br en_bar vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS precharge_1
|
||||
|
||||
.SUBCKT precharge_array_1 bl_0 br_0 bl_1 br_1 en_bar vdd
|
||||
Xpre_column_0 bl_0 br_0 en_bar vdd precharge_1
|
||||
Xpre_column_1 bl_1 br_1 en_bar vdd precharge_1
|
||||
.ENDS precharge_array_1
|
||||
*********************** "sense_amp" ******************************
|
||||
|
||||
.SUBCKT sense_amp bl br dout en vdd gnd
|
||||
|
||||
* SPICE3 file created from sense_amp.ext - technology: scmos
|
||||
|
||||
M1000 gnd en a_56_432# gnd n w=1.8u l=0.4u
|
||||
M1001 a_56_432# a_48_304# dout gnd n w=1.8u l=0.4u
|
||||
M1002 a_48_304# dout a_56_432# gnd n w=1.8u l=0.4u
|
||||
M1003 vdd a_48_304# dout vdd p w=3.6u l=0.4u
|
||||
M1004 a_48_304# dout vdd vdd p w=3.6u l=0.4u
|
||||
M1005 bl en dout vdd p w=4.8u l=0.4u
|
||||
M1006 a_48_304# en br vdd p w=4.8u l=0.4u
|
||||
|
||||
.ENDS
|
||||
|
||||
.SUBCKT sense_amp_array data_0 bl_0 br_0 data_1 bl_1 br_1 en vdd gnd
|
||||
Xsa_d0 bl_0 br_0 data_0 en vdd gnd sense_amp
|
||||
Xsa_d1 bl_1 br_1 data_1 en vdd gnd sense_amp
|
||||
.ENDS sense_amp_array
|
||||
*********************** Write_Driver ******************************
|
||||
.SUBCKT write_driver din bl br en vdd gnd
|
||||
|
||||
**** Inverter to conver Data_in to data_in_bar ******
|
||||
* din_bar = inv(din)
|
||||
M_1 din_bar din gnd gnd n W=0.8u L=0.4u
|
||||
M_2 din_bar din vdd vdd p W=1.4u L=0.4u
|
||||
|
||||
**** 2input nand gate follwed by inverter to drive BL ******
|
||||
* din_bar_gated = nand(en, din)
|
||||
M_3 din_bar_gated en net_7 gnd n W=1.4u L=0.4u
|
||||
M_4 net_7 din gnd gnd n W=1.4u L=0.4u
|
||||
M_5 din_bar_gated en vdd vdd p W=1.4u L=0.4u
|
||||
M_6 din_bar_gated din vdd vdd p W=1.4u L=0.4u
|
||||
* din_bar_gated_bar = inv(din_bar_gated)
|
||||
M_7 din_bar_gated_bar din_bar_gated vdd vdd p W=1.4u L=0.4u
|
||||
M_8 din_bar_gated_bar din_bar_gated gnd gnd n W=0.8u L=0.4u
|
||||
|
||||
**** 2input nand gate follwed by inverter to drive BR******
|
||||
* din_gated = nand(en, din_bar)
|
||||
M_9 din_gated en vdd vdd p W=1.4u L=0.4u
|
||||
M_10 din_gated en net_8 gnd n W=1.4u L=0.4u
|
||||
M_11 net_8 din_bar gnd gnd n W=1.4u L=0.4u
|
||||
M_12 din_gated din_bar vdd vdd p W=1.4u L=0.4u
|
||||
* din_gated_bar = inv(din_gated)
|
||||
M_13 din_gated_bar din_gated vdd vdd p W=1.4u L=0.4u
|
||||
M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
|
||||
|
||||
************************************************
|
||||
* pull down with en enable
|
||||
M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u
|
||||
M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u
|
||||
M_17 net_5 en gnd gnd n W=2.4u L=0.4u
|
||||
|
||||
|
||||
|
||||
.ENDS $ write_driver
|
||||
|
||||
.SUBCKT write_driver_array data_0 data_1 bl_0 br_0 bl_1 br_1 en vdd gnd
|
||||
Xwrite_driver0 data_0 bl_0 br_0 en vdd gnd write_driver
|
||||
Xwrite_driver1 data_1 bl_1 br_1 en vdd gnd write_driver
|
||||
.ENDS write_driver_array
|
||||
|
||||
* ptx M{0} {1} n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
|
||||
* ptx M{0} {1} p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
|
||||
.SUBCKT pinv_1 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_1
|
||||
|
||||
* ptx M{0} {1} n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
|
||||
.SUBCKT pnand2_1 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand2_1
|
||||
|
||||
.SUBCKT pnand3_1 A B C Z vdd gnd
|
||||
Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand3_1
|
||||
|
||||
.SUBCKT pinv_2 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_2
|
||||
|
||||
.SUBCKT pnand2_2 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand2_2
|
||||
|
||||
.SUBCKT pre2x4_1 in_0 in_1 out_0 out_1 out_2 out_3 vdd gnd
|
||||
Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_2
|
||||
Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_2
|
||||
Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_2
|
||||
Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_2
|
||||
Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_2
|
||||
Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_2
|
||||
XXpre2x4_nand_0 inbar_0 inbar_1 Z_0 vdd gnd pnand2_2
|
||||
XXpre2x4_nand_1 in_0 inbar_1 Z_1 vdd gnd pnand2_2
|
||||
XXpre2x4_nand_2 inbar_0 in_1 Z_2 vdd gnd pnand2_2
|
||||
XXpre2x4_nand_3 in_0 in_1 Z_3 vdd gnd pnand2_2
|
||||
.ENDS pre2x4_1
|
||||
|
||||
.SUBCKT pinv_3 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_3
|
||||
|
||||
.SUBCKT pnand3_2 A B C Z vdd gnd
|
||||
Mpnand3_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_pmos3 Z C vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos1 Z C net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos2 net1 B net2 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand3_nmos3 net2 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand3_2
|
||||
|
||||
.SUBCKT pre3x8_2 in_0 in_1 in_2 out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 vdd gnd
|
||||
Xpre_inv_0 in_0 inbar_0 vdd gnd pinv_3
|
||||
Xpre_inv_1 in_1 inbar_1 vdd gnd pinv_3
|
||||
Xpre_inv_2 in_2 inbar_2 vdd gnd pinv_3
|
||||
Xpre_nand_inv_0 Z_0 out_0 vdd gnd pinv_3
|
||||
Xpre_nand_inv_1 Z_1 out_1 vdd gnd pinv_3
|
||||
Xpre_nand_inv_2 Z_2 out_2 vdd gnd pinv_3
|
||||
Xpre_nand_inv_3 Z_3 out_3 vdd gnd pinv_3
|
||||
Xpre_nand_inv_4 Z_4 out_4 vdd gnd pinv_3
|
||||
Xpre_nand_inv_5 Z_5 out_5 vdd gnd pinv_3
|
||||
Xpre_nand_inv_6 Z_6 out_6 vdd gnd pinv_3
|
||||
Xpre_nand_inv_7 Z_7 out_7 vdd gnd pinv_3
|
||||
XXpre3x8_nand_0 inbar_0 inbar_1 inbar_2 Z_0 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_1 in_0 inbar_1 inbar_2 Z_1 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_2 inbar_0 in_1 inbar_2 Z_2 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_3 in_0 in_1 inbar_2 Z_3 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_4 inbar_0 inbar_1 in_2 Z_4 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_5 in_0 inbar_1 in_2 Z_5 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_6 inbar_0 in_1 in_2 Z_6 vdd gnd pnand3_2
|
||||
XXpre3x8_nand_7 in_0 in_1 in_2 Z_7 vdd gnd pnand3_2
|
||||
.ENDS pre3x8_2
|
||||
|
||||
.SUBCKT hierarchical_decoder_16rows_1 addr_0 addr_1 addr_2 addr_3 decode_0 decode_1 decode_2 decode_3 decode_4 decode_5 decode_6 decode_7 decode_8 decode_9 decode_10 decode_11 decode_12 decode_13 decode_14 decode_15 vdd gnd
|
||||
Xpre_0 addr_0 addr_1 out_0 out_1 out_2 out_3 vdd gnd pre2x4_1
|
||||
Xpre_1 addr_2 addr_3 out_4 out_5 out_6 out_7 vdd gnd pre2x4_1
|
||||
XDEC_NAND_0 out_0 out_4 Z_0 vdd gnd pnand2_1
|
||||
XDEC_NAND_4 out_0 out_5 Z_4 vdd gnd pnand2_1
|
||||
XDEC_NAND_8 out_0 out_6 Z_8 vdd gnd pnand2_1
|
||||
XDEC_NAND_12 out_0 out_7 Z_12 vdd gnd pnand2_1
|
||||
XDEC_NAND_1 out_1 out_4 Z_1 vdd gnd pnand2_1
|
||||
XDEC_NAND_5 out_1 out_5 Z_5 vdd gnd pnand2_1
|
||||
XDEC_NAND_9 out_1 out_6 Z_9 vdd gnd pnand2_1
|
||||
XDEC_NAND_13 out_1 out_7 Z_13 vdd gnd pnand2_1
|
||||
XDEC_NAND_2 out_2 out_4 Z_2 vdd gnd pnand2_1
|
||||
XDEC_NAND_6 out_2 out_5 Z_6 vdd gnd pnand2_1
|
||||
XDEC_NAND_10 out_2 out_6 Z_10 vdd gnd pnand2_1
|
||||
XDEC_NAND_14 out_2 out_7 Z_14 vdd gnd pnand2_1
|
||||
XDEC_NAND_3 out_3 out_4 Z_3 vdd gnd pnand2_1
|
||||
XDEC_NAND_7 out_3 out_5 Z_7 vdd gnd pnand2_1
|
||||
XDEC_NAND_11 out_3 out_6 Z_11 vdd gnd pnand2_1
|
||||
XDEC_NAND_15 out_3 out_7 Z_15 vdd gnd pnand2_1
|
||||
XDEC_INV_0 Z_0 decode_0 vdd gnd pinv_1
|
||||
XDEC_INV_1 Z_1 decode_1 vdd gnd pinv_1
|
||||
XDEC_INV_2 Z_2 decode_2 vdd gnd pinv_1
|
||||
XDEC_INV_3 Z_3 decode_3 vdd gnd pinv_1
|
||||
XDEC_INV_4 Z_4 decode_4 vdd gnd pinv_1
|
||||
XDEC_INV_5 Z_5 decode_5 vdd gnd pinv_1
|
||||
XDEC_INV_6 Z_6 decode_6 vdd gnd pinv_1
|
||||
XDEC_INV_7 Z_7 decode_7 vdd gnd pinv_1
|
||||
XDEC_INV_8 Z_8 decode_8 vdd gnd pinv_1
|
||||
XDEC_INV_9 Z_9 decode_9 vdd gnd pinv_1
|
||||
XDEC_INV_10 Z_10 decode_10 vdd gnd pinv_1
|
||||
XDEC_INV_11 Z_11 decode_11 vdd gnd pinv_1
|
||||
XDEC_INV_12 Z_12 decode_12 vdd gnd pinv_1
|
||||
XDEC_INV_13 Z_13 decode_13 vdd gnd pinv_1
|
||||
XDEC_INV_14 Z_14 decode_14 vdd gnd pinv_1
|
||||
XDEC_INV_15 Z_15 decode_15 vdd gnd pinv_1
|
||||
.ENDS hierarchical_decoder_16rows_1
|
||||
|
||||
.SUBCKT pinv_4 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_4
|
||||
|
||||
.SUBCKT pinv_5 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_5
|
||||
|
||||
.SUBCKT pnand2_3 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand2_3
|
||||
|
||||
.SUBCKT wordline_driver in_0 in_1 in_2 in_3 in_4 in_5 in_6 in_7 in_8 in_9 in_10 in_11 in_12 in_13 in_14 in_15 wl_0 wl_1 wl_2 wl_3 wl_4 wl_5 wl_6 wl_7 wl_8 wl_9 wl_10 wl_11 wl_12 wl_13 wl_14 wl_15 en_bar vdd gnd
|
||||
Xwl_driver_nand0 en_bar in_0 wl_bar_0 vdd gnd pnand2_3
|
||||
Xwl_driver_inv0 wl_bar_0 wl_0 vdd gnd pinv_4
|
||||
Xwl_driver_nand1 en_bar in_1 wl_bar_1 vdd gnd pnand2_3
|
||||
Xwl_driver_inv1 wl_bar_1 wl_1 vdd gnd pinv_4
|
||||
Xwl_driver_nand2 en_bar in_2 wl_bar_2 vdd gnd pnand2_3
|
||||
Xwl_driver_inv2 wl_bar_2 wl_2 vdd gnd pinv_4
|
||||
Xwl_driver_nand3 en_bar in_3 wl_bar_3 vdd gnd pnand2_3
|
||||
Xwl_driver_inv3 wl_bar_3 wl_3 vdd gnd pinv_4
|
||||
Xwl_driver_nand4 en_bar in_4 wl_bar_4 vdd gnd pnand2_3
|
||||
Xwl_driver_inv4 wl_bar_4 wl_4 vdd gnd pinv_4
|
||||
Xwl_driver_nand5 en_bar in_5 wl_bar_5 vdd gnd pnand2_3
|
||||
Xwl_driver_inv5 wl_bar_5 wl_5 vdd gnd pinv_4
|
||||
Xwl_driver_nand6 en_bar in_6 wl_bar_6 vdd gnd pnand2_3
|
||||
Xwl_driver_inv6 wl_bar_6 wl_6 vdd gnd pinv_4
|
||||
Xwl_driver_nand7 en_bar in_7 wl_bar_7 vdd gnd pnand2_3
|
||||
Xwl_driver_inv7 wl_bar_7 wl_7 vdd gnd pinv_4
|
||||
Xwl_driver_nand8 en_bar in_8 wl_bar_8 vdd gnd pnand2_3
|
||||
Xwl_driver_inv8 wl_bar_8 wl_8 vdd gnd pinv_4
|
||||
Xwl_driver_nand9 en_bar in_9 wl_bar_9 vdd gnd pnand2_3
|
||||
Xwl_driver_inv9 wl_bar_9 wl_9 vdd gnd pinv_4
|
||||
Xwl_driver_nand10 en_bar in_10 wl_bar_10 vdd gnd pnand2_3
|
||||
Xwl_driver_inv10 wl_bar_10 wl_10 vdd gnd pinv_4
|
||||
Xwl_driver_nand11 en_bar in_11 wl_bar_11 vdd gnd pnand2_3
|
||||
Xwl_driver_inv11 wl_bar_11 wl_11 vdd gnd pinv_4
|
||||
Xwl_driver_nand12 en_bar in_12 wl_bar_12 vdd gnd pnand2_3
|
||||
Xwl_driver_inv12 wl_bar_12 wl_12 vdd gnd pinv_4
|
||||
Xwl_driver_nand13 en_bar in_13 wl_bar_13 vdd gnd pnand2_3
|
||||
Xwl_driver_inv13 wl_bar_13 wl_13 vdd gnd pinv_4
|
||||
Xwl_driver_nand14 en_bar in_14 wl_bar_14 vdd gnd pnand2_3
|
||||
Xwl_driver_inv14 wl_bar_14 wl_14 vdd gnd pinv_4
|
||||
Xwl_driver_nand15 en_bar in_15 wl_bar_15 vdd gnd pnand2_3
|
||||
Xwl_driver_inv15 wl_bar_15 wl_15 vdd gnd pinv_4
|
||||
.ENDS wordline_driver
|
||||
|
||||
.SUBCKT pinv_6 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_6
|
||||
|
||||
.SUBCKT bank dout0_0 dout0_1 din0_0 din0_1 addr0_0 addr0_1 addr0_2 addr0_3 s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd
|
||||
Xbitcell_array bl0_0 br0_0 bl0_1 br0_1 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 vdd gnd bitcell_array_16x2_1
|
||||
Xprecharge_array0 bl0_0 br0_0 bl0_1 br0_1 p_en_bar0 vdd precharge_array_1
|
||||
Xsense_amp_array0 dout0_0 bl0_0 br0_0 dout0_1 bl0_1 br0_1 s_en0 vdd gnd sense_amp_array
|
||||
Xwrite_driver_array0 din0_0 din0_1 bl0_0 br0_0 bl0_1 br0_1 w_en0 vdd gnd write_driver_array
|
||||
Xrow_decoder0 addr0_0 addr0_1 addr0_2 addr0_3 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 vdd gnd hierarchical_decoder_16rows_1
|
||||
Xwordline_driver0 dec_out0_0 dec_out0_1 dec_out0_2 dec_out0_3 dec_out0_4 dec_out0_5 dec_out0_6 dec_out0_7 dec_out0_8 dec_out0_9 dec_out0_10 dec_out0_11 dec_out0_12 dec_out0_13 dec_out0_14 dec_out0_15 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 wl0_8 wl0_9 wl0_10 wl0_11 wl0_12 wl0_13 wl0_14 wl0_15 wl_en0 vdd gnd wordline_driver
|
||||
.ENDS bank
|
||||
|
||||
* ptx M{0} {1} p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
|
||||
.SUBCKT pinv_9 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pinv_9
|
||||
|
||||
* ptx M{0} {1} n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
|
||||
* ptx M{0} {1} p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
|
||||
.SUBCKT pinv_10 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
.ENDS pinv_10
|
||||
|
||||
.SUBCKT dff_buf_2 D Q Qb clk vdd gnd
|
||||
Xdff_buf_dff D qint clk vdd gnd dff
|
||||
Xdff_buf_inv1 qint Qb vdd gnd pinv_9
|
||||
Xdff_buf_inv2 Qb Q vdd gnd pinv_10
|
||||
.ENDS dff_buf_2
|
||||
|
||||
.SUBCKT dff_buf_array_2x1_1 din_0 din_1 dout_0 dout_bar_0 dout_1 dout_bar_1 clk vdd gnd
|
||||
Xdff_r0_c0 din_0 dout_0 dout_bar_0 clk vdd gnd dff_buf_2
|
||||
Xdff_r1_c0 din_1 dout_1 dout_bar_1 clk vdd gnd dff_buf_2
|
||||
.ENDS dff_buf_array_2x1_1
|
||||
|
||||
.SUBCKT pnand2_4 A B Z vdd gnd
|
||||
Mpnand2_pmos1 vdd A Z vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_pmos2 Z B vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos1 Z B net1 gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpnand2_nmos2 net1 A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pnand2_4
|
||||
|
||||
.SUBCKT pinv_11 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
.ENDS pinv_11
|
||||
|
||||
.SUBCKT pand2_4_1 A B Z vdd gnd
|
||||
Xpand2_nand A B zb_int vdd gnd pnand2_4
|
||||
Xpand2_inv zb_int Z vdd gnd pinv_11
|
||||
.ENDS pand2_4_1
|
||||
|
||||
.SUBCKT pinv_12 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_12
|
||||
|
||||
.SUBCKT pinv_13 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
.ENDS pinv_13
|
||||
|
||||
.SUBCKT pbuf_4_1 A Z vdd gnd
|
||||
Xbuf_inv1 A zb_int vdd gnd pinv_12
|
||||
Xbuf_inv2 zb_int Z vdd gnd pinv_13
|
||||
.ENDS pbuf_4_1
|
||||
|
||||
.SUBCKT pinv_14 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
.ENDS pinv_14
|
||||
|
||||
* ptx M{0} {1} n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
|
||||
|
||||
* ptx M{0} {1} p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
|
||||
|
||||
.SUBCKT pinv_15 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=25.6u l=0.4u pd=52.00u ps=52.00u as=25.60p ad=25.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
|
||||
.ENDS pinv_15
|
||||
|
||||
.SUBCKT pbuf_16_2 A Z vdd gnd
|
||||
Xbuf_inv1 A zb_int vdd gnd pinv_14
|
||||
Xbuf_inv2 zb_int Z vdd gnd pinv_15
|
||||
.ENDS pbuf_16_2
|
||||
|
||||
.SUBCKT pinv_16 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=3.2u l=0.4u pd=7.20u ps=7.20u as=3.20p ad=3.20p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
.ENDS pinv_16
|
||||
|
||||
* ptx M{0} {1} n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
|
||||
* ptx M{0} {1} p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
|
||||
|
||||
.SUBCKT pinv_17 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
.ENDS pinv_17
|
||||
|
||||
.SUBCKT pbuf_8_3 A Z vdd gnd
|
||||
Xbuf_inv1 A zb_int vdd gnd pinv_16
|
||||
Xbuf_inv2 zb_int Z vdd gnd pinv_17
|
||||
.ENDS pbuf_8_3
|
||||
|
||||
.SUBCKT pinv_18 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_18
|
||||
|
||||
.SUBCKT pinv_19 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=12.8u l=0.4u pd=26.40u ps=26.40u as=12.80p ad=12.80p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=6.4u l=0.4u pd=13.60u ps=13.60u as=6.40p ad=6.40p
|
||||
.ENDS pinv_19
|
||||
|
||||
.SUBCKT replica_pbitcell_1RW_0W_0R bl0 br0 wl0 vdd gnd
|
||||
Minverter_nmos_left Q vdd gnd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Minverter_nmos_right gnd Q vdd gnd n m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Minverter_pmos_left Q vdd vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
|
||||
Minverter_pmos_right vdd Q vdd vdd p m=1 w=0.6000000000000001u l=0.4u pd=2.00u ps=2.00u as=0.60p ad=0.60p
|
||||
Mreadwrite_nmos_left0 bl0 wl0 Q gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
Mreadwrite_nmos_right0 vdd wl0 br0 gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS replica_pbitcell_1RW_0W_0R
|
||||
|
||||
.SUBCKT replica_pbitcell bl0 br0 wl0 vdd gnd
|
||||
Xpbitcell bl0 br0 wl0 vdd gnd replica_pbitcell_1RW_0W_0R
|
||||
.ENDS replica_pbitcell
|
||||
|
||||
.SUBCKT bitcell_array_8x1_2 bl0_0 br0_0 wl0_0 wl0_1 wl0_2 wl0_3 wl0_4 wl0_5 wl0_6 wl0_7 vdd gnd
|
||||
Xbit_r0_c0 bl0_0 br0_0 wl0_0 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r1_c0 bl0_0 br0_0 wl0_1 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r2_c0 bl0_0 br0_0 wl0_2 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r3_c0 bl0_0 br0_0 wl0_3 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r4_c0 bl0_0 br0_0 wl0_4 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r5_c0 bl0_0 br0_0 wl0_5 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r6_c0 bl0_0 br0_0 wl0_6 vdd gnd pbitcell_1RW_0W_0R
|
||||
Xbit_r7_c0 bl0_0 br0_0 wl0_7 vdd gnd pbitcell_1RW_0W_0R
|
||||
.ENDS bitcell_array_8x1_2
|
||||
|
||||
.SUBCKT pinv_20 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_20
|
||||
|
||||
.SUBCKT delay_chain_1 in out vdd gnd
|
||||
Xdinv0 in dout_1 vdd gnd pinv_20
|
||||
Xdload_0_0 dout_1 n_0_0 vdd gnd pinv_20
|
||||
Xdload_0_1 dout_1 n_0_1 vdd gnd pinv_20
|
||||
Xdload_0_2 dout_1 n_0_2 vdd gnd pinv_20
|
||||
Xdinv1 dout_1 dout_2 vdd gnd pinv_20
|
||||
Xdload_1_0 dout_2 n_1_0 vdd gnd pinv_20
|
||||
Xdload_1_1 dout_2 n_1_1 vdd gnd pinv_20
|
||||
Xdload_1_2 dout_2 n_1_2 vdd gnd pinv_20
|
||||
Xdinv2 dout_2 dout_3 vdd gnd pinv_20
|
||||
Xdload_2_0 dout_3 n_2_0 vdd gnd pinv_20
|
||||
Xdload_2_1 dout_3 n_2_1 vdd gnd pinv_20
|
||||
Xdload_2_2 dout_3 n_2_2 vdd gnd pinv_20
|
||||
Xdinv3 dout_3 out vdd gnd pinv_20
|
||||
Xdload_3_0 out n_3_0 vdd gnd pinv_20
|
||||
Xdload_3_1 out n_3_1 vdd gnd pinv_20
|
||||
Xdload_3_2 out n_3_2 vdd gnd pinv_20
|
||||
.ENDS delay_chain_1
|
||||
|
||||
.SUBCKT pinv_21 A Z vdd gnd
|
||||
Mpinv_pmos Z A vdd vdd p m=1 w=1.6u l=0.4u pd=4.00u ps=4.00u as=1.60p ad=1.60p
|
||||
Mpinv_nmos Z A gnd gnd n m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
.ENDS pinv_21
|
||||
|
||||
* ptx M{0} {1} p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
|
||||
.SUBCKT replica_bitline_rw en out vdd gnd
|
||||
Xrbl_inv bl0_0 out vdd gnd pinv_21
|
||||
Mrbl_access_tx vdd delayed_en bl0_0 vdd p m=1 w=0.8u l=0.4u pd=2.40u ps=2.40u as=0.80p ad=0.80p
|
||||
Xdelay_chain en delayed_en vdd gnd delay_chain_1
|
||||
Xbitcell bl0_0 br0_0 delayed_en vdd gnd replica_pbitcell
|
||||
Xload bl0_0 br0_0 gnd gnd gnd gnd gnd gnd gnd gnd vdd gnd bitcell_array_8x1_2
|
||||
.ENDS replica_bitline_rw
|
||||
|
||||
.SUBCKT control_logic_rw csb web clk s_en w_en p_en_bar wl_en clk_buf vdd gnd
|
||||
Xctrl_dffs csb web cs_bar cs we_bar we clk_buf vdd gnd dff_buf_array_2x1_1
|
||||
Xclkbuf clk clk_buf vdd gnd pbuf_4_1
|
||||
Xinv_clk_bar clk_buf clk_bar vdd gnd pinv_18
|
||||
Xand2_gated_clk_bar cs clk_bar gated_clk_bar vdd gnd pand2_4_1
|
||||
Xand2_gated_clk_buf clk_buf cs gated_clk_buf vdd gnd pand2_4_1
|
||||
Xbuf_wl_en gated_clk_bar wl_en vdd gnd pbuf_16_2
|
||||
Xbuf_w_en_buf we w_en vdd gnd pbuf_8_3
|
||||
Xand2_rbl_in gated_clk_bar we_bar rbl_in vdd gnd pand2_4_1
|
||||
Xand2_pre_p_en gated_clk_buf we_bar pre_p_en vdd gnd pand2_4_1
|
||||
Xinv_p_en_bar pre_p_en p_en_bar vdd gnd pinv_19
|
||||
Xbuf_s_en pre_s_en s_en vdd gnd pbuf_8_3
|
||||
Xreplica_bitline rbl_in pre_s_en vdd gnd replica_bitline_rw
|
||||
.ENDS control_logic_rw
|
||||
|
||||
.SUBCKT sram_2_16_scn4m_subm DIN0[0] DIN0[1] ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] csb0 web0 clk0 DOUT0[0] DOUT0[1] vdd gnd
|
||||
Xbank0 DOUT0[0] DOUT0[1] BANK_DIN0[0] BANK_DIN0[1] A0[0] A0[1] A0[2] A0[3] s_en0 p_en_bar0 w_en0 wl_en0 vdd gnd bank
|
||||
Xcontrol0 csb0 web0 clk0 s_en0 w_en0 p_en_bar0 wl_en0 clk_buf0 vdd gnd control_logic_rw
|
||||
Xrow_address0 ADDR0[0] ADDR0[1] ADDR0[2] ADDR0[3] A0[0] A0[1] A0[2] A0[3] clk_buf0 vdd gnd row_addr_dff
|
||||
Xdata_dff0 DIN0[0] DIN0[1] BANK_DIN0[0] BANK_DIN0[1] clk_buf0 vdd gnd data_dff
|
||||
.ENDS sram_2_16_scn4m_subm
|
||||
|
|
@ -1,47 +0,0 @@
|
|||
// OpenRAM SRAM model
|
||||
// Words: 16
|
||||
// Word size: 2
|
||||
|
||||
module sram_2_16_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
|
||||
|
||||
parameter DATA_WIDTH = 2 ;
|
||||
parameter ADDR_WIDTH = 4 ;
|
||||
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
|
||||
parameter DELAY = 3 ;
|
||||
|
||||
inout [DATA_WIDTH-1:0] DATA;
|
||||
input [ADDR_WIDTH-1:0] ADDR;
|
||||
input CSb; // active low chip select
|
||||
input WEb; // active low write control
|
||||
input OEb; // active output enable
|
||||
input clk; // clock
|
||||
|
||||
reg [DATA_WIDTH-1:0] data_out ;
|
||||
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
|
||||
|
||||
// Tri-State Buffer control
|
||||
// output : When WEb = 1, oeb = 0, csb = 0
|
||||
assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
|
||||
|
||||
// Memory Write Block
|
||||
// Write Operation : When WEb = 0, CSb = 0
|
||||
always @ (posedge clk)
|
||||
begin : MEM_WRITE
|
||||
if ( !CSb && !WEb ) begin
|
||||
mem[ADDR] = DATA;
|
||||
$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
// Memory Read Block
|
||||
// Read Operation : When WEb = 1, CSb = 0
|
||||
always @ (posedge clk)
|
||||
begin : MEM_READ
|
||||
if (!CSb && WEb) begin
|
||||
data_out <= #(DELAY) mem[ADDR];
|
||||
$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
|
@ -1,321 +0,0 @@
|
|||
library (sram_2_16_scn4m_subm_TT_3p3V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 3.3 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_scn4m_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 69426.85;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -1,321 +0,0 @@
|
|||
library (sram_2_16_scn4m_subm_TT_5V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 5 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_scn4m_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 68347.21;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000179;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268",\
|
||||
"0.268, 0.268, 0.268");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004",\
|
||||
"0.004, 0.004, 0.004");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("2.46222038320038");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -1,321 +0,0 @@
|
|||
library (sram_2_16_scn4m_subm_TT_5p0V_25C_lib){
|
||||
delay_model : "table_lookup";
|
||||
time_unit : "1ns" ;
|
||||
voltage_unit : "1v" ;
|
||||
current_unit : "1mA" ;
|
||||
resistance_unit : "1kohm" ;
|
||||
capacitive_load_unit(1 ,fF) ;
|
||||
leakage_power_unit : "1mW" ;
|
||||
pulling_resistance_unit :"1kohm" ;
|
||||
operating_conditions(OC){
|
||||
process : 1.0 ;
|
||||
voltage : 5.0 ;
|
||||
temperature : 25;
|
||||
}
|
||||
|
||||
input_threshold_pct_fall : 50.0 ;
|
||||
output_threshold_pct_fall : 50.0 ;
|
||||
input_threshold_pct_rise : 50.0 ;
|
||||
output_threshold_pct_rise : 50.0 ;
|
||||
slew_lower_threshold_pct_fall : 10.0 ;
|
||||
slew_upper_threshold_pct_fall : 90.0 ;
|
||||
slew_lower_threshold_pct_rise : 10.0 ;
|
||||
slew_upper_threshold_pct_rise : 90.0 ;
|
||||
|
||||
nom_voltage : 5.0;
|
||||
nom_temperature : 25;
|
||||
nom_process : 1.0;
|
||||
default_cell_leakage_power : 0.0 ;
|
||||
default_leakage_power_density : 0.0 ;
|
||||
default_input_pin_cap : 1.0 ;
|
||||
default_inout_pin_cap : 1.0 ;
|
||||
default_output_pin_cap : 0.0 ;
|
||||
default_max_transition : 0.5 ;
|
||||
default_fanout_load : 1.0 ;
|
||||
default_max_fanout : 4.0 ;
|
||||
default_connection_class : universal ;
|
||||
|
||||
lu_table_template(CELL_TABLE){
|
||||
variable_1 : input_net_transition;
|
||||
variable_2 : total_output_net_capacitance;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("2.45605, 9.8242, 78.5936");
|
||||
}
|
||||
|
||||
lu_table_template(CONSTRAINT_TABLE){
|
||||
variable_1 : related_pin_transition;
|
||||
variable_2 : constrained_pin_transition;
|
||||
index_1("0.0125, 0.05, 0.4");
|
||||
index_2("0.0125, 0.05, 0.4");
|
||||
}
|
||||
|
||||
default_operating_conditions : OC;
|
||||
|
||||
|
||||
type (DATA){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 2;
|
||||
bit_from : 0;
|
||||
bit_to : 1;
|
||||
}
|
||||
|
||||
type (ADDR){
|
||||
base_type : array;
|
||||
data_type : bit;
|
||||
bit_width : 4;
|
||||
bit_from : 0;
|
||||
bit_to : 3;
|
||||
}
|
||||
|
||||
cell (sram_2_16_scn4m_subm){
|
||||
memory(){
|
||||
type : ram;
|
||||
address_width : 4;
|
||||
word_width : 2;
|
||||
}
|
||||
interface_timing : true;
|
||||
dont_use : true;
|
||||
map_only : true;
|
||||
dont_touch : true;
|
||||
area : 0;
|
||||
|
||||
leakage_power () {
|
||||
when : "CSb0";
|
||||
value : 0.000172;
|
||||
}
|
||||
cell_leakage_power : 0;
|
||||
bus(DIN0){
|
||||
bus_type : DATA;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
memory_write(){
|
||||
address : ADDR0;
|
||||
clocked_on : clk0;
|
||||
}
|
||||
pin(DIN0[1:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
bus(DOUT0){
|
||||
bus_type : DATA;
|
||||
direction : output;
|
||||
max_capacitance : 78.5936;
|
||||
min_capacitance : 2.45605;
|
||||
memory_read(){
|
||||
address : ADDR0;
|
||||
}
|
||||
pin(DOUT0[1:0]){
|
||||
timing(){
|
||||
timing_sense : non_unate;
|
||||
related_pin : "clk0";
|
||||
timing_type : rising_edge;
|
||||
cell_rise(CELL_TABLE) {
|
||||
values("0.079, 0.079, 0.079",\
|
||||
"0.079, 0.079, 0.079",\
|
||||
"0.079, 0.079, 0.079");
|
||||
}
|
||||
cell_fall(CELL_TABLE) {
|
||||
values("0.079, 0.079, 0.079",\
|
||||
"0.079, 0.079, 0.079",\
|
||||
"0.079, 0.079, 0.079");
|
||||
}
|
||||
rise_transition(CELL_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_transition(CELL_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bus(ADDR0){
|
||||
bus_type : ADDR;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
max_transition : 0.4;
|
||||
pin(ADDR0[3:0]){
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(CSb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(WEb0){
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
timing(){
|
||||
timing_type : setup_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009",\
|
||||
"0.009, 0.009, 0.009");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type : hold_rising;
|
||||
related_pin : "clk0";
|
||||
rise_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
fall_constraint(CONSTRAINT_TABLE) {
|
||||
values("0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001",\
|
||||
"0.001, 0.001, 0.001");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pin(clk0){
|
||||
clock : true;
|
||||
direction : input;
|
||||
capacitance : 9.8242;
|
||||
internal_power(){
|
||||
when : "!CSb0 & clk0 & !WEb0";
|
||||
rise_power(scalar){
|
||||
values("5.193773500000001");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.193773500000001");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "!CSb0 & !clk0 & WEb0";
|
||||
rise_power(scalar){
|
||||
values("5.193773500000001");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("5.193773500000001");
|
||||
}
|
||||
}
|
||||
internal_power(){
|
||||
when : "CSb0";
|
||||
rise_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
fall_power(scalar){
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"min_pulse_width";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0.0");
|
||||
}
|
||||
}
|
||||
timing(){
|
||||
timing_type :"minimum_period";
|
||||
related_pin : clk0;
|
||||
rise_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
fall_constraint(scalar) {
|
||||
values("0");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
@ -1,124 +0,0 @@
|
|||
|
||||
</ul>
|
||||
<link rel="stylesheet" href="static/index.css">
|
||||
|
||||
<button class="collapsible">files</button>
|
||||
<div class="content">
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<button class="collapsible">./files/test_files</button>
|
||||
<div class="content">
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.py</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.py">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm_TT_5V_25C.lib</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm_TT_5V_25C.lib">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm_TT_3p3V_25C.lib</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm_TT_3p3V_25C.lib">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.sp</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.sp">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.v</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.v">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm_TT_5p0V_25C.lib</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm_TT_5p0V_25C.lib">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.gds</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.gds">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.html</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.html">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">sram_2_16_scn4m_subm.lef</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/sram_2_16_scn4m_subm.lef">link</a>
|
||||
</div>
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<button class="collapsible">./files/test_files/testfolder</button>
|
||||
<div class="content">
|
||||
|
||||
<button class="collapsible">file2</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/testfolder/file2">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">file1</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/testfolder/file1">link</a>
|
||||
</div>
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<button class="collapsible">./files/test_files/testfolder2</button>
|
||||
<div class="content">
|
||||
|
||||
<button class="collapsible">file4</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/testfolder2/file4">link</a>
|
||||
</div>
|
||||
|
||||
<button class="collapsible">file3</button>
|
||||
<div class="content">
|
||||
<a href="./files/test_files/testfolder2/file3">link</a>
|
||||
</div>
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
|
||||
</div>
|
||||
|
||||
|
||||
<script type="text/javascript">
|
||||
var coll = document.getElementsByClassName("collapsible");
|
||||
var i;
|
||||
|
||||
for (i = 0; i < coll.length; i++) {
|
||||
coll[i].addEventListener("click", function() {
|
||||
this.classList.toggle("active");
|
||||
var content = this.nextElementSibling;
|
||||
if (content.style.display === "block") {
|
||||
content.style.display = "none";
|
||||
} else {
|
||||
content.style.display = "block";
|
||||
}
|
||||
});
|
||||
}
|
||||
</script>
|
||||
</ul>
|
||||
|
|
@ -1,25 +0,0 @@
|
|||
/* Style the button that is used to open and close the collapsible content */
|
||||
.collapsible {
|
||||
background-color: #eee;
|
||||
color: #444;
|
||||
cursor: pointer;
|
||||
padding: 18px;
|
||||
width: 100%;
|
||||
border: none;
|
||||
text-align: left;
|
||||
outline: none;
|
||||
font-size: 15px;
|
||||
}
|
||||
|
||||
/* Add a background color to the button if it is clicked on (add the .active class with JS), and when you move the mouse over it (hover) */
|
||||
.active, .collapsible:hover {
|
||||
background-color: #ccc;
|
||||
}
|
||||
|
||||
/* Style the collapsible content. Note: hidden by default */
|
||||
.content {
|
||||
padding: 0 18px;
|
||||
display: none;
|
||||
overflow: hidden;
|
||||
background-color: #f1f1f1;
|
||||
}
|
||||
|
|
@ -1,42 +0,0 @@
|
|||
|
||||
</ul>
|
||||
<link rel="stylesheet" href="static/index.css">
|
||||
|
||||
<button class="collapsible">files</button>
|
||||
<div class="content">
|
||||
{% for root, dir, files in os.walk(filedir) %}
|
||||
{% if root != filedir %}
|
||||
|
||||
|
||||
<button class="collapsible">{{ root }}</button>
|
||||
<div class="content">
|
||||
{% for f in files %}
|
||||
<button class="collapsible">{{ f }}</button>
|
||||
<div class="content">
|
||||
<a href="{{ root }}/{{ f }}">link</a>
|
||||
</div>
|
||||
{% endfor %}
|
||||
</div>
|
||||
|
||||
{% endif %}
|
||||
{% endfor %}
|
||||
</div>
|
||||
|
||||
|
||||
<script type="text/javascript">
|
||||
var coll = document.getElementsByClassName("collapsible");
|
||||
var i;
|
||||
|
||||
for (i = 0; i < coll.length; i++) {
|
||||
coll[i].addEventListener("click", function() {
|
||||
this.classList.toggle("active");
|
||||
var content = this.nextElementSibling;
|
||||
if (content.style.display === "block") {
|
||||
content.style.display = "none";
|
||||
} else {
|
||||
content.style.display = "block";
|
||||
}
|
||||
});
|
||||
}
|
||||
</script>
|
||||
</ul>
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
class table_gen:
|
||||
def __init__(self,name):
|
||||
self.name = name
|
||||
self.rows = []
|
||||
self.table_id = 'data'
|
||||
|
||||
def add_row(self,row):
|
||||
self.rows.append(row)
|
||||
|
||||
def gen_table_head(self):
|
||||
html = ''
|
||||
|
||||
html += '<thead>'
|
||||
html += '<tr>'
|
||||
for col in self.rows[0]:
|
||||
html += '<th>' + str(col) + '</th>'
|
||||
html += '</tr>'
|
||||
html += '</thead>'
|
||||
return html
|
||||
|
||||
def gen_table_body(self):
|
||||
html = ''
|
||||
|
||||
html += '<tbody>'
|
||||
html += '<tr>'
|
||||
for row in self.rows[1:]:
|
||||
html += '<tr>'
|
||||
for col in row:
|
||||
html += '<td>' + str(col) + '</td>'
|
||||
html += '</tr>'
|
||||
html += '</tr>'
|
||||
html += '</tbody>'
|
||||
return html
|
||||
|
||||
def to_html(self):
|
||||
|
||||
html = ''
|
||||
html += '<table id= \"'+self.table_id+'\">'
|
||||
html += self.gen_table_head()
|
||||
html += self.gen_table_body()
|
||||
html += '</table>'
|
||||
|
||||
return html
|
||||
|
|
@ -1,22 +0,0 @@
|
|||
from flask_table import *
|
||||
|
||||
class timing_and_current_data(Table):
|
||||
"""
|
||||
Set up timing and current table columns and title information
|
||||
"""
|
||||
parameter = Col('Parameter')
|
||||
min = Col('Min')
|
||||
max = Col('Max')
|
||||
units = Col('Units')
|
||||
|
||||
class timing_and_current_data_item(object):
|
||||
"""
|
||||
Define timing and current data row element
|
||||
"""
|
||||
def __init__(self, parameter, min, max, units):
|
||||
self.parameter = parameter
|
||||
self.min = min
|
||||
self.max = max
|
||||
self.units = units
|
||||
|
||||
|
||||
|
|
@ -107,13 +107,7 @@ def check_versions():
|
|||
# FIXME: Check versions of other tools here??
|
||||
# or, this could be done in each module (e.g. verify, characterizer, etc.)
|
||||
global OPTS
|
||||
|
||||
try:
|
||||
import flask_table
|
||||
OPTS.datasheet_gen = 1
|
||||
except:
|
||||
OPTS.datasheet_gen = 0
|
||||
|
||||
|
||||
try:
|
||||
import coverage
|
||||
OPTS.coverage = 1
|
||||
|
|
|
|||
|
|
@ -47,9 +47,7 @@ c = sram_config(word_size=OPTS.word_size,
|
|||
print("Words per row: {}".format(c.words_per_row))
|
||||
|
||||
#from parser import *
|
||||
output_extensions = ["sp","v","lib","py"]
|
||||
if OPTS.datasheet_gen:
|
||||
output_extensions.append("html")
|
||||
output_extensions = ["sp","v","lib","py","html"]
|
||||
if not OPTS.netlist_only:
|
||||
output_extensions.extend(["gds","lef"])
|
||||
output_files = ["{0}.{1}".format(OPTS.output_name,x) for x in output_extensions]
|
||||
|
|
|
|||
Loading…
Reference in New Issue