mirror of https://github.com/VLSIDA/OpenRAM.git
Add assert to lef and verilog unit test. Fix verilog files in golden results.
This commit is contained in:
Matt Guthaus
parent
a7dd62b0e5
commit
e210ef2a41
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@ -36,10 +36,7 @@ class lef_test(openram_test):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
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self.isdiff(lefname,golden)
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os.system("rm {0}".format(gdsname))
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os.system("rm {0}".format(lefname))
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self.assertTrue(self.isdiff(lefname,golden))
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globals.end_openram()
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@ -33,9 +33,7 @@ class verilog_test(openram_test):
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# let's diff the result with a golden model
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golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
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self.isdiff(vname,golden)
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os.system("rm {0}".format(vname))
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self.assertTrue(self.isdiff(vname,golden))
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globals.end_openram()
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@ -2,46 +2,60 @@
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// Words: 16
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// Word size: 2
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module sram_2_16_1_freepdk45(DATA,ADDR,CSb,WEb,OEb,clk);
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module sram_2_16_1_freepdk45(
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// Port 0: RW
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clk0,csb0,web0,ADDR0,DIN0,DOUT0
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);
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parameter DATA_WIDTH = 2 ;
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parameter ADDR_WIDTH = 4 ;
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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// FIXME: This delay is arbitrary.
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parameter DELAY = 3 ;
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inout [DATA_WIDTH-1:0] DATA;
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input [ADDR_WIDTH-1:0] ADDR;
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input CSb; // active low chip select
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input WEb; // active low write control
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input OEb; // active output enable
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input clk; // clock
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input clk0; // clock
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input csb0; // active low chip select
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input web0; // active low write control
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input [ADDR_WIDTH-1:0] ADDR0;
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input [DATA_WIDTH-1:0] DIN0;
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output [DATA_WIDTH-1:0] DOUT0;
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reg [DATA_WIDTH-1:0] data_out ;
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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reg csb0_reg;
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reg web0_reg;
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reg [ADDR_WIDTH-1:0] ADDR0_reg;
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reg [DATA_WIDTH-1:0] DIN0_reg;
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reg [DATA_WIDTH-1:0] DOUT0;
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// Tri-State Buffer control
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// output : When WEb = 1, oeb = 0, csb = 0
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assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
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// Memory Write Block
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// Write Operation : When WEb = 0, CSb = 0
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always @ (posedge clk)
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begin : MEM_WRITE
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if ( !CSb && !WEb ) begin
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mem[ADDR] = DATA;
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$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
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end
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// All inputs are registers
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always @(posedge clk0)
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begin
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csb0_reg = csb0;
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web0_reg = web0;
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ADDR0_reg = ADDR0;
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DIN0_reg = DIN0;
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DOUT0 = 2'bx;
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if ( !csb0_reg && web0_reg )
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$display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
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if ( !csb0_reg && !web0_reg )
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$display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
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end
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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// Memory Read Block
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// Read Operation : When WEb = 1, CSb = 0
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always @ (posedge clk)
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begin : MEM_READ
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if (!CSb && WEb) begin
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data_out <= #(DELAY) mem[ADDR];
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$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
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end
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// Memory Write Block Port 0
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// Write Operation : When web0 = 0, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_WRITE0
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if ( !csb0_reg && !web0_reg )
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mem[ADDR0_reg] = DIN0_reg;
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end
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// Memory Read Block Port 0
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// Read Operation : When web0 = 1, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_READ0
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if (!csb0_reg && web0_reg)
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DOUT0 <= #(DELAY) mem[ADDR0_reg];
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end
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endmodule
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@ -2,46 +2,60 @@
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// Words: 16
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// Word size: 2
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module sram_2_16_1_scn4m_subm(DATA,ADDR,CSb,WEb,OEb,clk);
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module sram_2_16_1_scn4m_subm(
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// Port 0: RW
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clk0,csb0,web0,ADDR0,DIN0,DOUT0
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);
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parameter DATA_WIDTH = 2 ;
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parameter ADDR_WIDTH = 4 ;
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parameter RAM_DEPTH = 1 << ADDR_WIDTH;
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// FIXME: This delay is arbitrary.
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parameter DELAY = 3 ;
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inout [DATA_WIDTH-1:0] DATA;
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input [ADDR_WIDTH-1:0] ADDR;
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input CSb; // active low chip select
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input WEb; // active low write control
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input OEb; // active output enable
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input clk; // clock
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input clk0; // clock
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input csb0; // active low chip select
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input web0; // active low write control
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input [ADDR_WIDTH-1:0] ADDR0;
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input [DATA_WIDTH-1:0] DIN0;
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output [DATA_WIDTH-1:0] DOUT0;
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reg [DATA_WIDTH-1:0] data_out ;
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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reg csb0_reg;
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reg web0_reg;
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reg [ADDR_WIDTH-1:0] ADDR0_reg;
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reg [DATA_WIDTH-1:0] DIN0_reg;
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reg [DATA_WIDTH-1:0] DOUT0;
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// Tri-State Buffer control
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// output : When WEb = 1, oeb = 0, csb = 0
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assign DATA = (!CSb && !OEb && WEb) ? data_out : 2'bz;
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// Memory Write Block
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// Write Operation : When WEb = 0, CSb = 0
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always @ (posedge clk)
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begin : MEM_WRITE
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if ( !CSb && !WEb ) begin
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mem[ADDR] = DATA;
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$display($time," Writing %m ABUS=%b DATA=%b",ADDR,DATA);
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end
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// All inputs are registers
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always @(posedge clk0)
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begin
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csb0_reg = csb0;
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web0_reg = web0;
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ADDR0_reg = ADDR0;
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DIN0_reg = DIN0;
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DOUT0 = 2'bx;
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if ( !csb0_reg && web0_reg )
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$display($time," Reading %m ADDR0=%b DOUT0=%b",ADDR0_reg,mem[ADDR0_reg]);
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if ( !csb0_reg && !web0_reg )
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$display($time," Writing %m ADDR0=%b DIN0=%b",ADDR0_reg,DIN0_reg);
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end
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reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
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// Memory Read Block
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// Read Operation : When WEb = 1, CSb = 0
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always @ (posedge clk)
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begin : MEM_READ
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if (!CSb && WEb) begin
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data_out <= #(DELAY) mem[ADDR];
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$display($time," Reading %m ABUS=%b DATA=%b",ADDR,mem[ADDR]);
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end
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// Memory Write Block Port 0
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// Write Operation : When web0 = 0, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_WRITE0
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if ( !csb0_reg && !web0_reg )
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mem[ADDR0_reg] = DIN0_reg;
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end
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// Memory Read Block Port 0
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// Read Operation : When web0 = 1, csb0 = 0
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always @ (negedge clk0)
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begin : MEM_READ0
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if (!csb0_reg && web0_reg)
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DOUT0 <= #(DELAY) mem[ADDR0_reg];
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end
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endmodule
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