mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed syntax error referring to column mux
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parent
3d3f54aa86
commit
3c4d559308
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@ -235,10 +235,9 @@ class bank(design.design):
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# Place the col decoder left aligned with wordline driver plus halfway under row decoder
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# Place the col decoder left aligned with row decoder (x_offset doesn't change)
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# Below the bitcell array with well spacing
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x_offset = self.central_bus_width[port] + self.wordline_driver.width \
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+ self.column_decoder.width + self.col_addr_bus_width
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x_offset = self.central_bus_width[port] + self.wordline_driver.width
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if self.col_addr_size > 0:
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x_offset += self.column_decoder.width + self.col_addr_bus_width
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y_offset = self.m2_gap + self.column_decoder.height
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else:
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y_offset = 0
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@ -295,9 +294,9 @@ class bank(design.design):
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# UPPER RIGHT QUADRANT
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# Place the col decoder right aligned with wordline driver plus halfway under row decoder
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# Above the bitcell array with a well spacing
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x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width \
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+ self.column_decoder.width + self.col_addr_bus_width
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x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width
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if self.col_addr_size > 0:
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x_offset += self.column_decoder.width + self.col_addr_bus_width
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y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap
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else:
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y_offset = self.bitcell_array.height
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