mirror of https://github.com/VLSIDA/OpenRAM.git
Convert wordline driver to use sized pdriver
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parent
091b4e4c62
commit
8f56953af0
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@ -446,7 +446,8 @@ class bank(design.design):
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self.add_mod(self.row_decoder)
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self.wordline_driver = factory.create(module_type="wordline_driver",
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rows=self.num_rows)
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rows=self.num_rows,
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cols=self.num_cols)
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self.add_mod(self.wordline_driver)
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self.inv = factory.create(module_type="pinv")
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@ -15,10 +15,11 @@ class wordline_driver(design.design):
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Generates the wordline-driver to drive the bitcell
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"""
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def __init__(self, name, rows):
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def __init__(self, name, rows, cols):
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design.design.__init__(self, name)
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self.rows = rows
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self.cols = cols
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -52,7 +53,9 @@ class wordline_driver(design.design):
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# This is just used for measurements,
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# so don't add the module
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self.inv = factory.create(module_type="pinv")
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self.inv = factory.create(module_type="pdriver",
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fanout=self.cols,
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neg_polarity=True)
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self.add_mod(self.inv)
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self.inv_no_output = factory.create(module_type="pinv",
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@ -22,7 +22,7 @@ class wordline_driver_test(openram_test):
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# check wordline driver for single port
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debug.info(2, "Checking driver")
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tx = wordline_driver.wordline_driver(name="wld1", rows=8)
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tx = wordline_driver.wordline_driver(name="wld1", rows=8, cols=32)
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self.local_check(tx)
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# check wordline driver for multi-port
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@ -33,7 +33,7 @@ class wordline_driver_test(openram_test):
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factory.reset()
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debug.info(2, "Checking driver (multi-port case)")
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tx = wordline_driver.wordline_driver(name="wld2", rows=8)
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tx = wordline_driver.wordline_driver(name="wld2", rows=8, cols=64)
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self.local_check(tx)
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globals.end_openram()
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