mirror of https://github.com/VLSIDA/OpenRAM.git
complete log file generation
This commit is contained in:
Jesse Cirimelli-Low
parent
e210ef2a41
commit
87380a4801
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@ -14,20 +14,51 @@ def check(check,str):
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index) = inspect.getouterframes(inspect.currentframe())[1]
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if not check:
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sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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log("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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assert 0
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def error(str,return_value=0):
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(frame, filename, line_number, function_name, lines,
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index) = inspect.getouterframes(inspect.currentframe())[1]
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sys.stderr.write("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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log("ERROR: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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assert return_value==0
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def warning(str):
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(frame, filename, line_number, function_name, lines,
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index) = inspect.getouterframes(inspect.currentframe())[1]
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sys.stderr.write("WARNING: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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log("WARNING: file {0}: line {1}: {2}\n".format(os.path.basename(filename),line_number,str))
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def print_raw(str):
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print(str)
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log(str)
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def log(str):
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try:
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if log.create_file:
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compile_log = open(globals.OPTS.output_path + globals.OPTS.output_name + '.log',"w+")
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log.create_file = 0
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else:
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compile_log = open(globals.OPTS.output_path + globals.OPTS.output_name + '.log',"a")
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if len(log.setup_output) != 0:
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for line in log.setup_output:
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compile_log.write(line)
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log.setup_output = []
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compile_log.write(str + '\n')
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except:
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log.setup_out.append(str + "\n")
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#use a static list of strings to store messages until the global paths are set up
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log.setup_output = []
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log.create_file = 1
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def info(lev, str):
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from globals import OPTS
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if (OPTS.debug_level >= lev):
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@ -71,26 +71,26 @@ def print_banner():
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if OPTS.is_unit_test:
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return
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print("|==============================================================================|")
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debug.print_raw("|==============================================================================|")
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name = "OpenRAM Compiler"
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print("|=========" + name.center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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print("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
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print("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
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print("|=========" + "University of California Santa Cruz".center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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print("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
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print("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|")
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print("|=========" + "Oklahoma State University".center(60) + "=========|")
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print("|=========" + " ".center(60) + "=========|")
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debug.print_raw("|=========" + name.center(60) + "=========|")
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debug.print_raw("|=========" + " ".center(60) + "=========|")
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debug.print_raw("|=========" + "VLSI Design and Automation Lab".center(60) + "=========|")
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debug.print_raw("|=========" + "Computer Science and Engineering Department".center(60) + "=========|")
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debug.print_raw("|=========" + "University of California Santa Cruz".center(60) + "=========|")
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debug.print_raw("|=========" + " ".center(60) + "=========|")
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debug.print_raw("|=========" + "VLSI Computer Architecture Research Group".center(60) + "=========|")
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debug.print_raw("|=========" + "Electrical and Computer Engineering Department".center(60) + "=========|")
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debug.print_raw("|=========" + "Oklahoma State University".center(60) + "=========|")
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debug.print_raw("|=========" + " ".center(60) + "=========|")
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user_info = "Usage help: openram-user-group@ucsc.edu"
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print("|=========" + user_info.center(60) + "=========|")
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debug.print_raw("|=========" + user_info.center(60) + "=========|")
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dev_info = "Development help: openram-dev-group@ucsc.edu"
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print("|=========" + dev_info.center(60) + "=========|")
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debug.print_raw("|=========" + dev_info.center(60) + "=========|")
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temp_info = "Temp dir: {}".format(OPTS.openram_temp)
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print("|=========" + temp_info.center(60) + "=========|")
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print("|=========" + "See LICENSE for license info".center(60) + "=========|")
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print("|==============================================================================|")
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debug.print_raw("|=========" + temp_info.center(60) + "=========|")
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debug.print_raw("|=========" + "See LICENSE for license info".center(60) + "=========|")
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debug.print_raw("|==============================================================================|")
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def check_versions():
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@ -397,7 +397,7 @@ def print_time(name, now_time, last_time=None, indentation=2):
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time = str(round((now_time-last_time).total_seconds(),1)) + " seconds"
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else:
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time = now_time.strftime('%m/%d/%Y %H:%M:%S')
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print("{0} {1}: {2}".format("*"*indentation,name,time))
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debug.print_raw("{0} {1}: {2}".format("*"*indentation,name,time))
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def report_status():
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@ -413,20 +413,20 @@ def report_status():
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if not OPTS.tech_name:
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debug.error("Tech name must be specified in config file.")
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print("Technology: {0}".format(OPTS.tech_name))
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print("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
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print("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
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debug.print_raw("Technology: {0}".format(OPTS.tech_name))
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debug.print_raw("Total size: {} bits".format(OPTS.word_size*OPTS.num_words*OPTS.num_banks))
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debug.print_raw("Word size: {0}\nWords: {1}\nBanks: {2}".format(OPTS.word_size,
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OPTS.num_words,
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OPTS.num_banks))
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print("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports,
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debug.print_raw("RW ports: {0}\nR-only ports: {1}\nW-only ports: {2}".format(OPTS.num_rw_ports,
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OPTS.num_r_ports,
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OPTS.num_w_ports))
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if OPTS.netlist_only:
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print("Netlist only mode (no physical design is being done).")
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debug.print_raw("Netlist only mode (no physical design is being done).")
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if not OPTS.inline_lvsdrc:
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print("DRC/LVS/PEX is only run on the top-level design.")
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debug.print_raw("DRC/LVS/PEX is only run on the top-level design.")
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if not OPTS.check_lvsdrc:
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print("DRC/LVS/PEX is completely disabled.")
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debug.print_raw("DRC/LVS/PEX is completely disabled.")
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@ -44,15 +44,16 @@ from sram_config import sram_config
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# Configure the SRAM organization
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c = sram_config(word_size=OPTS.word_size,
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num_words=OPTS.num_words)
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print("Words per row: {}".format(c.words_per_row))
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debug.print_raw("Words per row: {}".format(c.words_per_row))
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#from parser import *
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output_extensions = ["sp","v","lib","py","html"]
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output_extensions = ["sp","v","lib","py","html","log"]
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if not OPTS.netlist_only:
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output_extensions.extend(["gds","lef"])
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output_files = ["{0}{1}.{2}".format(OPTS.output_path,OPTS.output_name,x) for x in output_extensions]
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print("Output files are: ")
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print(*output_files,sep="\n")
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debug.print_raw("Output files are: ")
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for path in output_files:
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debug.print_raw(path)
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from sram import sram
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@ -65,21 +65,21 @@ class sram():
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# Write the layout
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start_time = datetime.datetime.now()
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gdsname = OPTS.output_path + self.s.name + ".gds"
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print("GDS: Writing to {0}".format(gdsname))
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debug.print_raw("GDS: Writing to {0}".format(gdsname))
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self.gds_write(gdsname)
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print_time("GDS", datetime.datetime.now(), start_time)
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# Create a LEF physical model
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start_time = datetime.datetime.now()
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lefname = OPTS.output_path + self.s.name + ".lef"
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print("LEF: Writing to {0}".format(lefname))
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debug.print_raw("LEF: Writing to {0}".format(lefname))
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self.lef_write(lefname)
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print_time("LEF", datetime.datetime.now(), start_time)
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# Save the spice file
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start_time = datetime.datetime.now()
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spname = OPTS.output_path + self.s.name + ".sp"
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print("SP: Writing to {0}".format(spname))
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debug.print_raw("SP: Writing to {0}".format(spname))
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self.sp_write(spname)
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print_time("Spice writing", datetime.datetime.now(), start_time)
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@ -98,14 +98,14 @@ class sram():
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# Characterize the design
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start_time = datetime.datetime.now()
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from characterizer import lib
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print("LIB: Characterizing... ")
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debug.print_raw("LIB: Characterizing... ")
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if OPTS.analytical_delay:
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print("Using analytical delay models (no characterization)")
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debug.print_raw("Using analytical delay models (no characterization)")
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else:
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if OPTS.spice_name!="":
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print("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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debug.print_raw("Performing simulation-based characterization with {}".format(OPTS.spice_name))
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if OPTS.trim_netlist:
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print("Trimming netlist to speed up characterization.")
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debug.print_raw("Trimming netlist to speed up characterization.")
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lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file)
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print_time("Characterization", datetime.datetime.now(), start_time)
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@ -114,20 +114,20 @@ class sram():
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start_time = datetime.datetime.now()
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from shutil import copyfile
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copyfile(OPTS.config_file + '.py', OPTS.output_path + OPTS.output_name + '.py')
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print("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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debug.print_raw("Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py'))
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print_time("Config", datetime.datetime.now(), start_time)
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# Write the datasheet
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start_time = datetime.datetime.now()
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from datasheet_gen import datasheet_gen
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dname = OPTS.output_path + self.s.name + ".html"
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print("Datasheet: Writing to {0}".format(dname))
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debug.print_raw("Datasheet: Writing to {0}".format(dname))
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datasheet_gen.datasheet_write(self.s,dname)
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print_time("Datasheet", datetime.datetime.now(), start_time)
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# Write a verilog model
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start_time = datetime.datetime.now()
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vname = OPTS.output_path + self.s.name + ".v"
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print("Verilog: Writing to {0}".format(vname))
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debug.print_raw("Verilog: Writing to {0}".format(vname))
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self.verilog_write(vname)
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print_time("Verilog", datetime.datetime.now(), start_time)
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