mirror of https://github.com/VLSIDA/OpenRAM.git
Provide more stats in -v output
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514f6fda27
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@ -236,18 +236,19 @@ class router(router_tech):
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This will try to separate all grid pins by the supplied number of separation
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tracks (default is to prevent adjacency).
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"""
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debug.info(1,"Separating adjacent pins.")
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# Commented out to debug with SCMOS
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#if separation==0:
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# return
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pin_names = self.pin_groups.keys()
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for pin_name1 in pin_names:
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for pin_name2 in pin_names:
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if pin_name1==pin_name2:
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continue
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self.separate_adjacent_pin(pin_name1, pin_name2, separation)
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pin_names = self.pin_groups.keys()
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for i,pin_name1 in enumerate(pin_names):
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for j,pin_name2 in enumerate(pin_names):
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if i==j:
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continue
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if i>j:
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return
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self.separate_adjacent_pin(pin_name1, pin_name2, separation)
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def separate_adjacent_pin(self, pin_name1, pin_name2, separation):
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"""
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Go through all of the pin groups and check if any other pin group is
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@ -256,13 +257,18 @@ class router(router_tech):
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Try to do this intelligently to keep th pins enclosed.
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"""
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debug.info(1,"Comparing {0} and {1} adjacency".format(pin_name1, pin_name2))
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removed_grids = 0
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for index1,pg1 in enumerate(self.pin_groups[pin_name1]):
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for index2,pg2 in enumerate(self.pin_groups[pin_name2]):
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adj_grids = pg1.adjacent_grids(pg2, separation)
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removed_grids += len(adj_grids)
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# These should have the same length, so...
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if len(adj_grids)>0:
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debug.info(3,"Adjacent grids {0} {1} adj={2}".format(index1,index2,adj_grids))
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self.remove_adjacent_grid(pg1, pg2, adj_grids)
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debug.info(1,"Removed {} adjacent grids.".format(removed_grids))
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def remove_adjacent_grid(self, pg1, pg2, adj_grids):
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"""
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@ -101,7 +101,7 @@ class supply_router(router):
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# These are the wire tracks
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wire_tracks = self.supply_rail_tracks[pin_name]
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routed_count=0
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for pg in self.pin_groups[pin_name]:
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if pg.is_routed():
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continue
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@ -109,6 +109,7 @@ class supply_router(router):
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# First, check if we just overlap, if so, we are done.
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overlap_grids = wire_tracks & pg.grids
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if len(overlap_grids)>0:
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routed_count += 1
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pg.set_routed()
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continue
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@ -116,7 +117,7 @@ class supply_router(router):
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#pg.create_simple_overlap_enclosure(pg.grids)
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#pg.add_enclosure(self.cell)
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debug.info(1,"Routed {} simple overlap pins".format(routed_count))
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def finalize_supply_rails(self, name):
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"""
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@ -366,8 +367,8 @@ class supply_router(router):
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"""
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remaining_components = sum(not x.is_routed() for x in self.pin_groups[pin_name])
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debug.info(1,"Routing {0} with {1} pin components to route.".format(pin_name,
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remaining_components))
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debug.info(1,"Maze routing {0} with {1} pin components to connect.".format(pin_name,
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remaining_components))
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for index,pg in enumerate(self.pin_groups[pin_name]):
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if pg.is_routed():
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