mirror of https://github.com/VLSIDA/OpenRAM.git
Added delay chain sizing for rise/fall delays. Disabled to some sizes being having very large fanouts.
This commit is contained in:
Hunter Nichols
parent
6e47de3f9b
commit
3716030a23
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@ -208,7 +208,7 @@ class delay(simulation):
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trig_slew_low = 0.1 * self.vdd_voltage
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targ_slew_high = 0.9 * self.vdd_voltage
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if 'delay' in delay_name:
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trig_dir="RISE"
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trig_dir="RISE" #FALL
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trig_val = half_vdd
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targ_val = half_vdd
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trig_name = trig_clk_name
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@ -429,6 +429,7 @@ class delay(simulation):
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delay_names = ["{0}{1}".format(mname,port) for mname in self.delay_meas_names]
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delay_names = [mname for mname in self.delay_meas_names]
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delays = self.parse_values(delay_names, port, 1e9) # scale delays to ns
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debug.info(2,"Delay values = {}".format(delays))
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if not self.check_valid_delays(tuple(delays.values())):
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return (False,{})
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result[port].update(delays)
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@ -646,18 +647,6 @@ class delay(simulation):
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# slew=0.04
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# self.try_period(target_period, feasible_delay_lh, feasible_delay_hl)
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# sys.exit(1)
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#For debugging, skips characterization and returns dummy values.
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# char_data = self.get_empty_measure_data_dict()
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# i = 1.0
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# for slew in slews:
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# for load in loads:
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# for k,v in char_data.items():
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# char_data[k].append(i)
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# i+=1.0
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# char_data["min_period"] = i
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# char_data["leakage_power"] = i+1.0
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# return char_data
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# 1) Find a feasible period and it's corresponding delays using the trimmed array.
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feasible_delays = self.find_feasible_period()
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@ -834,34 +823,6 @@ class delay(simulation):
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return (sram_data,port_data)
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# delay_lh = []
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# delay_hl = []
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# slew_lh = []
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# slew_hl = []
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# for slew in slews:
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# for load in loads:
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# self.set_load_slew(load,slew)
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# bank_delay = sram.analytical_delay(self.vdd_voltage, self.slew,self.load)
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# # Convert from ps to ns
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# delay_lh.append(bank_delay.delay/1e3)
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# delay_hl.append(bank_delay.delay/1e3)
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# slew_lh.append(bank_delay.slew/1e3)
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# slew_hl.append(bank_delay.slew/1e3)
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# power = self.analytical_power()
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# sram_data = { "min_period": 0,
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# "leakage_power": power.leakage}
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# port_data = [{"delay_lh": delay_lh,
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# "delay_hl": delay_hl,
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# "slew_lh": slew_lh,
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# "slew_hl": slew_hl,
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# "read0_power": power.dynamic,
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# "read1_power": power.dynamic,
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# "write0_power": power.dynamic,
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# "write1_power": power.dynamic,
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# }]
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# return (sram_data,port_data)
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def analytical_power(self, slews, loads):
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"""Get the dynamic and leakage power from the SRAM"""
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@ -103,13 +103,17 @@ class control_logic(design.design):
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delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
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bitcell_loads = int(math.ceil(self.num_rows / 2.0))
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self.replica_bitline = replica_bitline(delay_stages_heuristic, delay_fanout_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
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self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
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if self.sram != None and not self.is_sen_timing_okay():
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#Resize the delay chain (by instantiating a new rbl) if the analytical timing failed.
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#This resizes to match fall and rise delays, can make the delay chain weird sizes.
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#stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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#self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
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#This resizes based on total delay.
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delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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self.replica_bitline = replica_bitline(delay_stages, delay_fanout, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
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self.sen_delay = self.get_delay_to_sen() #get the new timing
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self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
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self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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self.add_mod(self.replica_bitline)
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@ -124,16 +128,20 @@ class control_logic(design.design):
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delay_stages = 6
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else:
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delay_stages = 4
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return (delay_stages, delay_fanout)
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def is_sen_timing_okay(self):
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self.wl_delay = self.get_delay_to_wl()
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self.sen_delay = self.get_delay_to_sen()
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self.wl_delay_rise,self.wl_delay_fall = self.get_delays_to_wl()
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self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen()
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self.wl_delay = self.wl_delay_rise+self.wl_delay_fall
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self.sen_delay = self.sen_delay_rise+self.sen_delay_fall
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#The sen delay must always be bigger than than the wl delay. This decides how much larger the sen delay must be before
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#a re-size is warranted.
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if self.wl_delay*self.wl_timing_tolerance >= self.sen_delay:
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if (self.wl_delay_rise*self.wl_timing_tolerance >= self.sen_delay_rise or
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self.wl_delay_fall*self.wl_timing_tolerance >= self.sen_delay_fall):
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return False
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else:
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return True
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@ -155,7 +163,59 @@ class control_logic(design.design):
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#Fanout can be varied as well but is a little more complicated but potentially optimal.
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debug.info(1, "Setting delay chain to {} stages with {} fanout to match {} delay".format(delay_stages, delay_fanout, required_delay))
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return (delay_stages, delay_fanout)
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def get_dynamic_delay_fanout_list(self, previous_stages, previous_fanout):
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"""Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
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previous_delay_chain_delay = (previous_fanout+1+self.parasitic_inv_delay)*previous_stages
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debug.info(2, "Previous delay chain produced {} delay units".format(previous_delay_chain_delay))
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fanout_rise = fanout_fall = 2 # This can be anything >=2
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#The delay chain uses minimum sized inverters. There are (fanout+1)*stages inverters and each
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#inverter adds 1 unit of delay (due to minimum size). This also depends on the pinv value
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required_delay_fall = self.wl_delay_fall*self.wl_timing_tolerance - (self.sen_delay_fall-previous_delay_chain_delay/2)
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required_delay_rise = self.wl_delay_rise*self.wl_timing_tolerance - (self.sen_delay_rise-previous_delay_chain_delay/2)
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debug.info(2,"Required delays from chain: fall={}, rise={}".format(required_delay_fall,required_delay_rise))
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#The stages need to be equal (or at least a even number of stages with matching rise/fall delays)
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while True:
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stages_fall = self.calculate_stages_with_fixed_fanout(required_delay_fall,fanout_fall)
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stages_rise = self.calculate_stages_with_fixed_fanout(required_delay_rise,fanout_rise)
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debug.info(1,"Fall stages={}, rise stages={}".format(stages_fall,stages_rise))
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if stages_fall == stages_rise:
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break
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elif abs(stages_fall-stages_rise) == 1:
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break
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#There should also be a condition to make sure the fanout does not get too large.
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#Otherwise, increase the fanout of delay with the most stages, calculate new stages
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elif stages_fall>stages_rise:
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fanout_fall+=1
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else:
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fanout_rise+=1
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total_stages = max(stages_fall,stages_rise)*2
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debug.info(1, "New Delay chain: stages={}, fanout_rise={}, fanout_fall={}".format(total_stages, fanout_rise, fanout_fall))
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#Creates interleaved fanout list of rise/fall delays. Assumes fall is the first stage.
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stage_list = [fanout_fall if i%2==0 else fanout_rise for i in range(total_stages)]
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return stage_list
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def calculate_stages_with_fixed_fanout(self, required_delay, fanout):
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from math import ceil
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#Delay being negative is not an error. It implies that any amount of stages would have a negative effect on the overall delay
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if required_delay<=3: #3 is the minimum delay per stage.
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return 1
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delay_stages = ceil(required_delay/(fanout+1+self.parasitic_inv_delay))
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return delay_stages
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def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall):
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"""Produces a list of fanouts which determine the size of the delay chain. List length is the number of stages.
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Assumes the first stage is falling.
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"""
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stage_list = []
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for i in range(total_stages):
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if i%2 == 0:
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stage_list.append()
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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@ -641,14 +701,14 @@ class control_logic(design.design):
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width=pin.width())
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def get_delay_to_wl(self):
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def get_delays_to_wl(self):
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"""Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
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debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
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stage_efforts = self.determine_wordline_stage_efforts()
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clk_to_wl_rise,clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay)
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total_delay = clk_to_wl_rise + clk_to_wl_fall
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debug.info(1, "Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise, clk_to_wl_fall,total_delay))
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return total_delay
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return clk_to_wl_rise,clk_to_wl_fall
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def determine_wordline_stage_efforts(self):
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@ -670,7 +730,7 @@ class control_logic(design.design):
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return stage_effort_list
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def get_delay_to_sen(self):
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def get_delays_to_sen(self):
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"""Get the delay (in delay units) of the clk to a sense amp enable.
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This does not incorporate the delay of the replica bitline.
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"""
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@ -679,7 +739,7 @@ class control_logic(design.design):
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clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(stage_efforts, self.parasitic_inv_delay)
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total_delay = clk_to_sen_rise + clk_to_sen_fall
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debug.info(1, "Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise, clk_to_sen_fall,total_delay))
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return total_delay
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return clk_to_sen_rise, clk_to_sen_fall
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def determine_sa_enable_stage_efforts(self):
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"""Follows the clock signal to the sense amp enable signal adding each stages stage effort to a list"""
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@ -15,12 +15,11 @@ class replica_bitline(design.design):
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line and rows is the height of the replica bit loads.
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"""
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def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
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def __init__(self, delay_fanout_list, bitcell_loads, name="replica_bitline"):
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design.design.__init__(self, name)
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self.bitcell_loads = bitcell_loads
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self.delay_stages = delay_stages
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self.delay_fanout = delay_fanout
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self.delay_fanout_list = delay_fanout_list
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self.create_netlist()
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if not OPTS.netlist_only:
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@ -95,7 +94,7 @@ class replica_bitline(design.design):
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# FIXME: The FO and depth of this should be tuned
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from delay_chain import delay_chain
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self.delay_chain = delay_chain([self.delay_fanout]*self.delay_stages)
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self.delay_chain = delay_chain(self.delay_fanout_list)
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self.add_mod(self.delay_chain)
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self.inv = pinv()
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