mirror of https://github.com/VLSIDA/OpenRAM.git
Fix p_en_bar at top level. Change default scn4m period to 10ns.
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c45f990413
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@ -143,7 +143,7 @@ class sram_base(design):
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self.control_bus_names[port] = ["clk_buf{}".format(port)]
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wen = "w_en{}".format(port)
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sen = "s_en{}".format(port)
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pen = "p_en{}".format(port)
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pen = "p_en_bar{}".format(port)
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if self.port_id[port] == "r":
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self.control_bus_names[port].extend([sen, pen])
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elif self.port_id[port] == "w":
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@ -293,7 +293,7 @@ class sram_base(design):
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for port in self.read_ports:
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temp.append("s_en{0}".format(port))
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for port in self.read_ports:
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temp.append("p_en{0}".format(port))
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temp.append("p_en_bar{0}".format(port))
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for port in self.write_ports:
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temp.append("w_en{0}".format(port))
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for port in self.all_ports:
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@ -419,7 +419,7 @@ class sram_base(design):
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if port in self.write_ports:
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temp.append("w_en{}".format(port))
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if port in self.read_ports:
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temp.append("p_en{}".format(port))
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temp.append("p_en_bar{}".format(port))
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temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
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self.connect_inst(temp)
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@ -240,7 +240,7 @@ spice["fet_models"] = { "TT" : [SPICE_MODEL_DIR+"/nom/pmos.sp",SPICE_MODEL_DIR+"
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#spice stimulus related variables
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spice["feasible_period"] = 5 # estimated feasible period in ns
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spice["feasible_period"] = 10 # estimated feasible period in ns
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spice["supply_voltages"] = [4.5, 5.0, 5.5] # Supply voltage corners in [Volts]
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spice["nom_supply_voltage"] = 5.0 # Nominal supply voltage in [Volts]
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spice["rise_time"] = 0.05 # rise time in [Nano-seconds]
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