mirror of https://github.com/VLSIDA/OpenRAM.git
Move pnand2 output to allow input pin access on M2
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8fba32ca12
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5209619987
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@ -192,26 +192,33 @@ class pnand2(pgate.pgate):
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""" Route the Z output """
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# PMOS1 drain
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pmos_pin = self.pmos1_inst.get_pin("D")
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top_pin_offset = pmos_pin.center()
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# NMOS2 drain
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nmos_pin = self.nmos2_inst.get_pin("D")
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nmos_pin = self.nmos2_inst.get_pin("D")
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bottom_pin_offset = nmos_pin.center()
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# Output pin
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mid_offset = vector(nmos_pin.center().x,self.inputA_yoffset)
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out_offset = vector(nmos_pin.center().x + self.m1_pitch,self.inputA_yoffset)
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# Midpoints of the L routes go horizontal first then vertical
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mid1_offset = vector(out_offset.x, top_pin_offset.y)
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mid2_offset = vector(out_offset.x, bottom_pin_offset.y)
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=pmos_pin.center())
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=nmos_pin.center())
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self.add_contact_center(layers=("metal1", "via1", "metal2"),
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offset=mid_offset,
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offset=out_offset,
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rotate=90)
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# PMOS1 to mid-drain to NMOS2 drain
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self.add_path("metal2",[pmos_pin.bc(), mid_offset, nmos_pin.uc()])
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self.add_path("metal2",[top_pin_offset, mid1_offset, out_offset, mid2_offset, bottom_pin_offset])
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# This extends the output to the edge of the cell
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self.add_layout_pin_rect_center(text="Z",
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layer="metal1",
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offset=mid_offset,
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offset=out_offset,
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width=contact.m1m2.first_layer_height,
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height=contact.m1m2.first_layer_width)
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