mirror of https://github.com/VLSIDA/OpenRAM.git
Change Netlisting to submodules to reflect what time is of
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@ -78,7 +78,7 @@ class sram_base(design):
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if not OPTS.is_unit_test:
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print_time("Netlisting",datetime.now(), start_time)
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print_time("Submodules",datetime.now(), start_time)
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def create_layout(self):
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