mirror of https://github.com/VLSIDA/OpenRAM.git
Changed method of determining number of inverters.
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8ea85e3e65
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@ -14,6 +14,7 @@ class pdriver(pgate.pgate):
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unique_id = 1
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inv_list = []
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inv_inst_list = []
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calc_size_list = []
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def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
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@ -29,8 +30,7 @@ class pdriver(pgate.pgate):
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self.compute_sizes()
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if name=="":
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name = "pdriver_{0}_{1}_{2}".format(self.stage_effort, self.num_inv,
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pdriver.unique_id)
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name = "pdriver_{0}_{1}_".format(self.num_inv, pdriver.unique_id)
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pdriver.unique_id += 1
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pgate.pgate.__init__(self, name)
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@ -47,20 +47,54 @@ class pdriver(pgate.pgate):
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neg_polarity = True
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self.num_inv = len(self.size_list)
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else:
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# rho with p_inv = 1
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rho = 3.59
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num_stages = max(1, int(math.log1p(self.stage_effort)/math.log1p(rho)))
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# find the number of stages
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c_prev = int(round(self.c_load/self.stage_effort))
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num_stages = 1
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while c_prev > 1: #stop when the first stage is 1
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c_prev = int(round(c_prev/self.stage_effort))
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num_stages+=1
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# find inv_num and compute sizes
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if self.neg_polarity:
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if (num_stages % 2 == 0): # if num_stages is even
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self.num_inv = int(num_stages)+1
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self.diff_polarity(num_stages=num_stages)
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else: # if num_stages is odd
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self.num_inv = int(num_stages)
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self.same_polarity(num_stages=num_stages)
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else: # positive polarity
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if (num_stages % 2 == 0):
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self.num_inv = int(num_stages)
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self.same_polarity(num_stages=num_stages)
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else:
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self.num_inv = int(num_stages)+1
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self.diff_polarity(num_stages=num_stages)
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def same_polarity(self, num_stages):
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self.num_inv = num_stages
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# compute sizes
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c_prev = self.c_load
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for x in range(self.num_inv-1,-1,-1):
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c_prev = int(round(c_prev/self.stage_effort))
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self.calc_size_list.append(c_prev)
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def diff_polarity(self, num_stages):
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# find which delay is smaller
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delay_below = ((num_stages-1)*(self.c_load**(1/num_stages-1))) + num_stages-1
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delay_above = ((num_stages+1)*(self.c_load**(1/num_stages+1))) + num_stages+1
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if (delay_above < delay_below):
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# recompute stage_effort for this delay
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self.num_inv = num_stages+1
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polarity_stage_effort = self.c_load**(1/self.num_inv)
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else:
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self.num_inv = num_stages-1
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polarity_stage_effort = self.c_load**(1/self.num_inv)
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# compute sizes
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c_prev = self.c_load
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for x in range(self.num_inv-1,-1,-1):
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c_prev = int(round(c_prev/polarity_stage_effort))
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self.calc_size_list.append(c_prev)
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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@ -88,13 +122,11 @@ class pdriver(pgate.pgate):
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self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
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self.add_mod(self.inv_list[x])
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else: # find inv sizes
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# work backwards to find the size of each stage
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for x in range(self.num_inv-1, -1, -1):
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c_in = max(1, int(round(self.c_load/self.stage_effort,0)))
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self.c_load = c_in
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self.inv_list.append(pinv(size=c_in, height=self.row_height))
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for x in range(len(self.calc_size_list)):
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self.inv_list.append(pinv(size=self.calc_size_list[x], height=self.row_height))
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self.add_mod(self.inv_list[x])
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def create_insts(self):
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for x in range(1,self.num_inv+1):
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# Create first inverter
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@ -24,10 +24,10 @@ class pdriver_test(openram_test):
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# a tests the error message for specifying conflicting conditions
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#a = pdriver.pdriver(c_load = 4,size_list = [1,2,4,8])
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b = pdriver.pdriver(size_list = [1,2,4,8])
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c = pdriver.pdriver(c_load = 4)
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d = pdriver.pdriver(c_load = 4, neg_polarity = True)
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c = pdriver.pdriver(c_load = 50)
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d = pdriver.pdriver(c_load = 50, neg_polarity = True)
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e = pdriver.pdriver(c_load = 64)
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f = pdriver.pdriver(c_load = 64, neg_polarity = False)
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f = pdriver.pdriver(c_load = 64, neg_polarity = True)
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#self.local_check(a)
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self.local_check(b)
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self.local_check(c)
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