Change path to wire_path for Anaconda package conflict

compiler/base/hierarchy_layout.py

@@ -320,17 +320,17 @@ class layout():
     def add_path(self, layer, coordinates, width=None):
         """Connects a routing path on given layer,coordinates,width."""
         debug.info(4,"add path " + str(layer) + " " + str(coordinates))
-        import path
+        import wire_path
         # NOTE: (UNTESTED) add_path(...) is currently not used
         # negative layers indicate "unused" layers in a given technology
         #layer_num = techlayer[layer]
         #if layer_num >= 0:
         #    self.objs.append(geometry.path(layer_num, coordinates, width))
 
-        path.path(obj=self,
-                  layer=layer, 
-                  position_list=coordinates, 
-                  width=width)
+        wire_path.wire_path(obj=self,
+                            layer=layer, 
+                            position_list=coordinates, 
+                            width=width)
 
     def add_route(self, layers, coordinates, layer_widths):
         """Connects a routing path on given layer,coordinates,width. The

compiler/base/wire.py

@@ -1,9 +1,9 @@
 from tech import drc
 import debug
-from path import path
+from wire_path import wire_path
 from sram_factory import factory
 
-class wire(path):
+class wire(wire_path):
     """ 
     Object metal wire; given the layer type
     Add a wire of minimium metal width between a set of points. 
@@ -26,7 +26,7 @@ class wire(path):
         self.create_rectilinear()
         self.create_vias()
         self.create_rectangles()
-        # wires and paths should not be offset to (0,0)
+        # wires and wire_paths should not be offset to (0,0)
 
     def setup_layers(self):
         (horiz_layer, via_layer, vert_layer) = self.layer_stack

compiler/base/wire_path.py

@@ -18,12 +18,12 @@ def create_rectilinear_route(my_list):
     my_list.append(vector(pl[-1]))
     return my_list
         
-class path():
+class wire_path():
     """
-    Object metal path; given the layer type
-    Add a path of minimium metal width between a set of points. 
+    Object metal wire_path; given the layer type
+    Add a wire_path of minimium metal width between a set of points. 
     The points should be rectilinear to control the bend points. If
-    not, it will always go down first. The points are the center of the path.
+    not, it will always go down first. The points are the center of the wire_path.
     If width is not given, it uses minimum layer width.
     """
     def __init__(self, obj, layer, position_list, width=None):
@@ -44,7 +44,7 @@ class path():
         self.create_rectilinear()
         self.connect_corner()
         self.create_rectangles()
-        # wires and paths should not be offset to (0,0)
+        # wires and wire_paths should not be offset to (0,0)
 
     def create_rectilinear(self):
         """ Add intermediate nodes if it isn't rectilinear. Also skip
@@ -52,7 +52,7 @@ class path():
         self.position_list = create_rectilinear_route(self.position_list)
 
     def connect_corner(self):
-        """ Add a corner square at every corner of the path."""
+        """ Add a corner square at every corner of the wire_path."""
         from itertools import tee,islice
         nwise = lambda g,n=2: zip(*(islice(g,i,None) for i,g in enumerate(tee(g,n))))
         threewise=nwise(self.position_list,3)

compiler/pgates/ptx.py

@@ -3,7 +3,6 @@ import debug
 from tech import drc, spice
 from vector import vector
 from globals import OPTS
-import path
 from sram_factory import factory
 
 class ptx(design.design):

compiler/tests/03_path_test.py

@@ -13,7 +13,7 @@ class path_test(openram_test):
 
     def runTest(self):
         globals.init_openram("config_20_{0}".format(OPTS.tech_name))
-        import path
+        import wire_path
         import tech
         import design
 
@@ -27,7 +27,7 @@ class path_test(openram_test):
                          [0, 3 * min_space ],
                          [0, 6 * min_space ]]
         w = design.design("path_test0")
-        path.path(w,layer_stack, position_list)
+        wire_path.wire_path(w,layer_stack, position_list)
         self.local_drc_check(w)
 
 
@@ -44,7 +44,7 @@ class path_test(openram_test):
                              [-1 * min_space, 0]]
         position_list  = [[x+min_space, y+min_space] for x,y in old_position_list]
         w = design.design("path_test1")
-        path.path(w,layer_stack, position_list)
+        wire_path.wire_path(w,layer_stack, position_list)
         self.local_drc_check(w)
 
         min_space = 2 * tech.drc["minwidth_metal2"]
@@ -60,7 +60,7 @@ class path_test(openram_test):
                              [-1 * min_space, 0]]
         position_list  = [[x-min_space, y-min_space] for x,y in old_position_list]
         w = design.design("path_test2")
-        path.path(w, layer_stack, position_list)
+        wire_path.wire_path(w, layer_stack, position_list)
         self.local_drc_check(w)
 
         min_space = 2 * tech.drc["minwidth_metal3"]
@@ -77,7 +77,7 @@ class path_test(openram_test):
         # run on the reverse list
         position_list.reverse()
         w = design.design("path_test3")
-        path.path(w, layer_stack, position_list)
+        wire_path.wire_path(w, layer_stack, position_list)
         self.local_drc_check(w)
 
         globals.end_openram()