mirror of https://github.com/VLSIDA/OpenRAM.git
Change dout to negative clock edge relative
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@ -329,7 +329,7 @@ class lib:
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self.lib.write(" timing(){ \n")
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self.lib.write(" timing_sense : non_unate; \n")
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self.lib.write(" related_pin : \"clk{0}\"; \n".format(read_port))
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self.lib.write(" timing_type : rising_edge; \n")
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self.lib.write(" timing_type : negative_edge; \n")
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self.lib.write(" cell_rise(CELL_TABLE) {\n")
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self.write_values(self.char_port_results[read_port]["delay_lh"],len(self.loads)," ")
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self.lib.write(" }\n") # rise delay
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