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Update stage effort of clk_buf_driver

This commit is contained in:
Matt Guthaus 2019-01-25 14:22:37 -08:00
parent 6f32bac1a2
commit 1afd4341bd
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/control_logic.py
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@ -833,7 +833,7 @@ class control_logic(design.design):
#Calculate the load on wl_en within the module and add it to external load
external_cout = self.sram.get_wl_en_cin()
#First stage is the clock buffer
stage_effort_list += self.clkbuf.get_stage_efforts(external_cout, is_clk_bar_rise)
stage_effort_list += self.clk_buf_driver.get_stage_efforts(external_cout, is_clk_bar_rise)
last_stage_is_rise = stage_effort_list[-1].is_rise
#Then ask the sram for the other path delays (from the bank)