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OpenRAM
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Don't always add all 3 types of contorl. Add write and read only port lists.

This commit is contained in:
Matt Guthaus 2018-11-16 15:03:12 -08:00
parent b13d938ea8
commit 8f28f4fde5
2 changed files with 8 additions and 2 deletions
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6
compiler/base/design.py
View File

@ -65,8 +65,12 @@ class design(hierarchy_design):
self.readwrite_ports = []
# These are the read/write and write-only port indices
self.write_ports = []
# These are the write-only port indices.
self.writeonly_ports = []
# These are teh read/write and read-only port indice
self.read_ports = []
# These are the read-only port indices.
self.readonly_ports = []
# These are all the ports
self.all_ports = list(range(total_ports))
@ -78,9 +82,11 @@ class design(hierarchy_design):
port_number += 1
for port in range(OPTS.num_w_ports):
self.write_ports.append(port_number)
self.writeonly_ports.append(port_number)
port_number += 1
for port in range(OPTS.num_r_ports):
self.read_ports.append(port_number)
self.readonly_ports.append(port_number)
port_number += 1
def analytical_power(self, proc, vdd, temp, load):

4
compiler/sram_base.py
View File

@ -226,12 +226,12 @@ class sram_base(design):
words_per_row=self.words_per_row,
port_type="rw")
self.add_mod(self.control_logic_rw)
if len(self.write_ports)>0:
if len(self.writeonly_ports)>0:
self.control_logic_w = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
port_type="w")
self.add_mod(self.control_logic_w)
if len(self.read_ports)>0:
if len(self.readonly_ports)>0:
self.control_logic_r = self.mod_control_logic(num_rows=self.num_rows,
words_per_row=self.words_per_row,
port_type="r")