mirror of https://github.com/VLSIDA/OpenRAM.git
Move row addr dffs to top of bank to prevent addr route problems
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@ -73,8 +73,9 @@ class sram_1bank(sram_base):
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self.control_logic_insts[port].place(control_pos[port])
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# The row address bits are placed above the control logic aligned on the right.
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# Or just below the top of the bank, whichever is greater.
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row_addr_pos[port] = vector(self.control_logic_insts[port].rx() - self.row_addr_dff_insts[port].width,
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self.control_logic_insts[port].uy())
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max(self.control_logic_insts[port].uy(), self.bank_inst.ul().y - self.row_addr_dff_insts[port].height))
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self.row_addr_dff_insts[port].place(row_addr_pos[port])
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# Add the col address flops below the bank to the left of the lower-left of bank array
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@ -103,8 +104,9 @@ class sram_1bank(sram_base):
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self.control_logic_insts[port].place(control_pos[port], mirror="MY")
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# The row address bits are placed above the control logic aligned on the left.
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# Or just below the top of the bank, whichever is greater.
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row_addr_pos[port] = vector(control_pos[port].x - self.control_logic_insts[port].width + self.row_addr_dff_insts[port].width,
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self.control_logic_insts[port].uy())
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max(self.control_logic_insts[port].uy(), self.bank_inst.ul().y - self.row_addr_dff_insts[port].height))
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self.row_addr_dff_insts[port].place(row_addr_pos[port], mirror="MY")
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# Add the col address flops above the bank to the right of the upper-right of bank array
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