luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity

Corretct modules for add_inst

Browse Source
This commit is contained in:
Matt Guthaus
2018-11-26 15:35:29 -08:00
parent b440031855
commit dd79fc560b
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/control_logic.py
+2 -2
View File
@@ -249,7 +249,7 @@ class control_logic(design.design):
self.connect_inst(["clk","clk_buf","vdd","gnd"])
self.gated_clk_inst = self.add_inst(name="gated_clkbuf",
mod=self.pbuf1)
mod=self.nand2)
self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"])
def place_clkbuf_row(self,row):
@@ -360,7 +360,7 @@ class control_logic(design.design):
# input: we, gated_clk output: pre_w_en
if self.port_type == "rw":
self.pre_w_en_inst = self.add_inst(name="and_pre_w_en",
mod=self.pand2)
mod=self.and2)
self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"])
input_name = "pre_w_en"
else: