mirror of https://github.com/VLSIDA/OpenRAM.git
Add netlist only mode to new pgates
This commit is contained in:
Matt Guthaus
parent
2eff166527
commit
b440031855
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@ -4,8 +4,9 @@ from tech import drc, parameter
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import debug
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import contact
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from pinv import pinv
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from pbuf import pbuf
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from pand2 import pand2
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from pnand2 import pnand2
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from pnand3 import pnand3
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from pinvbuf import pinvbuf
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from dff_inv import dff_inv
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from dff_inv_array import dff_inv_array
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@ -71,22 +72,30 @@ class control_logic(design.design):
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self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1)
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self.add_mod(self.ctrl_dff_array)
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self.and2 = pand2(height=dff_height)
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self.add_mod(self.and2)
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self.nand2 = pnand2(height=dff_height)
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self.add_mod(self.nand2)
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self.nand3 = pnand3(height=dff_height)
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self.add_mod(self.nand3)
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# Special gates: inverters for buffering
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# Size the clock for the number of rows (fanout)
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clock_driver_size = max(1,int(self.num_rows/4))
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self.clkbuf = pinvbuf(clock_driver_size,height=dff_height)
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self.clkbuf = pbuf(size=clock_driver_size, height=dff_height)
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self.add_mod(self.clkbuf)
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self.inv = self.inv1 = pinv(size=1, height=dff_height)
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self.add_mod(self.inv1)
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self.inv2 = pinv(size=4, height=dff_height)
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self.add_mod(self.inv2)
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self.inv8 = pinv(size=16, height=dff_height)
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self.add_mod(self.inv8)
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self.pbuf8 = pbuf(size=8, height=dff_height)
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self.add_mod(self.pbuf8)
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self.pbuf1 = pbuf(size=1, height=dff_height)
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self.add_mod(self.pbuf1)
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# self.inv = self.inv1 = pinv(size=1, height=dff_height)
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# self.add_mod(self.inv1)
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# self.inv2 = pinv(size=4, height=dff_height)
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# self.add_mod(self.inv2)
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# self.inv8 = pinv(size=16, height=dff_height)
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# self.add_mod(self.inv8)
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if (self.port_type == "rw") or (self.port_type == "r"):
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from importlib import reload
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@ -157,7 +166,7 @@ class control_logic(design.design):
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def create_instances(self):
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""" Create all the instances """
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self.create_dffs()
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self.create_clk_row()
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self.create_clk_rows()
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.create_we_row()
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if (self.port_type == "rw") or (self.port_type == "r"):
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@ -177,8 +186,10 @@ class control_logic(design.design):
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row = 0
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# Add the logic on the right of the bus
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self.place_clk_row(row=row) # clk is a double-high cell
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row += 2
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self.place_clkbuf_row(row=row)
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row += 1
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self.place_gated_clk_row(row=row)
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row += 1
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if (self.port_type == "rw") or (self.port_type == "w"):
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self.place_we_row(row=row)
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height = self.w_en_inst.uy()
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@ -219,11 +230,11 @@ class control_logic(design.design):
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""" Create the replica bitline """
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self.rbl_inst=self.add_inst(name="replica_bitline",
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mod=self.replica_bitline)
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self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"])
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self.connect_inst(["pre_p_en", "pre_s_en", "vdd", "gnd"])
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def place_rbl(self,row):
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""" Place the replica bitline """
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y_off = row * self.inv1.height + 2*self.m1_pitch
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y_off = row * self.nand2.height + 2*self.m1_pitch
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# Add the RBL above the rows
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# Add to the right of the control rows and routing channel
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@ -231,30 +242,38 @@ class control_logic(design.design):
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self.rbl_inst.place(self.replica_bitline_offset)
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def create_clk_row(self):
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""" Create the multistage clock buffer """
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def create_clk_rows(self):
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""" Create the multistage and gated clock buffer """
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self.clkbuf_inst = self.add_inst(name="clkbuf",
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mod=self.clkbuf)
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self.connect_inst(["clk","clk_buf_bar","clk_buf","vdd","gnd"])
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self.connect_inst(["clk","clk_buf","vdd","gnd"])
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def place_clk_row(self,row):
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self.gated_clk_inst = self.add_inst(name="gated_clkbuf",
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mod=self.pbuf1)
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self.connect_inst(["cs","clk_buf","gated_clk","vdd","gnd"])
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def place_clkbuf_row(self,row):
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""" Place the multistage clock buffer below the control flops """
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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clkbuf_offset = vector(x_off,y_off)
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self.clkbuf_inst.place(clkbuf_offset)
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offset = vector(x_off,y_off)
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self.clkbuf_inst.place(offset)
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self.row_end_inst.append(self.clkbuf_inst)
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def place_gatedclk_row(self,row):
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""" Place the gated clk logic below the control flops """
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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offset = vector(x_off,y_off)
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self.gated_clk_inst.place(offset)
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self.row_end_inst.append(self.gated_clk_inst)
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def create_rbl_in_row(self):
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self.rbl_in_bar_inst=self.add_inst(name="nand2_rbl_in_bar",
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mod=self.nand2)
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self.connect_inst(["clk_buf_bar", "cs", "rbl_in_bar", "vdd", "gnd"])
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# input: rbl_in_bar, output: rbl_in
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self.rbl_in_inst=self.add_inst(name="inv_rbl_in",
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mod=self.inv1)
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self.connect_inst(["rbl_in_bar", "rbl_in", "vdd", "gnd"])
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# input: gated_clk, we_bar, output: pre_p_en
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self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
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mod=self.and2)
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self.connect_inst(["gated_clk", "we_bar", "pre_p_en", "vdd", "gnd"])
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def place_rbl_in_row(self,row):
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@ -262,28 +281,20 @@ class control_logic(design.design):
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(y_off,mirror)=self.get_offset(row)
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self.rbl_in_bar_offset = vector(x_off, y_off)
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self.rbl_in_bar_inst.place(offset=self.rbl_in_bar_offset,
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mirror=mirror)
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x_off += self.nand2.width
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self.pre_p_en_offset = vector(x_off, y_off)
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self.pre_p_en_inst.place(offset=self.pre_p_en_offset,
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mirror=mirror)
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x_off += self.and2.width
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self.rbl_in_offset = vector(x_off, y_off)
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self.rbl_in_inst.place(offset=self.rbl_in_offset,
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mirror=mirror)
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self.row_end_inst.append(self.rbl_in_inst)
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self.row_end_inst.append(self.pre_p_en_inst)
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def create_sen_row(self):
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""" Create the sense enable buffer. """
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# input: pre_s_en, output: pre_s_en_bar
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self.pre_s_en_bar_inst=self.add_inst(name="inv_pre_s_en_bar",
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mod=self.inv2)
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self.connect_inst(["pre_s_en", "pre_s_en_bar", "vdd", "gnd"])
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# BUFFER INVERTERS FOR S_EN
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# input: input: pre_s_en_bar, output: s_en
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self.s_en_inst=self.add_inst(name="inv_s_en",
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mod=self.inv8)
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self.connect_inst(["pre_s_en_bar", "s_en", "vdd", "gnd"])
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# BUFFER FOR S_EN
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# input: pre_s_en, output: s_en
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self.s_en_inst=self.add_inst(name="buf_s_en",
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mod=self.pbuf8)
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self.connect_inst(["pre_s_en", "s_en", "vdd", "gnd"])
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def place_sen_row(self,row):
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"""
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@ -293,11 +304,6 @@ class control_logic(design.design):
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x_off = self.ctrl_dff_array.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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self.pre_s_en_bar_offset = vector(x_off, y_off)
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self.pre_s_en_bar_inst.place(offset=self.pre_s_en_bar_offset,
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mirror=mirror)
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x_off += self.inv2.width
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self.s_en_offset = vector(x_off, y_off)
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self.s_en_inst.place(offset=self.s_en_offset,
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mirror=mirror)
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@ -341,9 +347,9 @@ class control_logic(design.design):
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def get_offset(self,row):
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""" Compute the y-offset and mirroring """
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y_off = row*self.inv1.height
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y_off = row*self.nand2.height
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if row % 2:
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y_off += self.inv1.height
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y_off += self.nand2.height
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mirror="MX"
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else:
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mirror="R0"
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@ -351,60 +357,36 @@ class control_logic(design.design):
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return (y_off,mirror)
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def create_we_row(self):
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# input: WE, CS output: w_en_bar
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# input: we, gated_clk output: pre_w_en
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if self.port_type == "rw":
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nand_mod = self.nand3
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temp = ["clk_buf_bar", "cs", "we", "w_en_bar", "vdd", "gnd"]
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self.pre_w_en_inst = self.add_inst(name="and_pre_w_en",
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mod=self.pand2)
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self.connect_inst(["we", "gated_clk", "pre_w_en", "vdd", "gnd"])
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input_name = "pre_w_en"
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else:
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nand_mod = self.nand2
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temp = ["clk_buf_bar", "cs", "w_en_bar", "vdd", "gnd"]
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self.w_en_bar_inst = self.add_inst(name="nand3_w_en_bar",
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mod=nand_mod)
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self.connect_inst(temp)
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# input: w_en_bar, output: pre_w_en
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self.pre_w_en_inst = self.add_inst(name="inv_pre_w_en",
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mod=self.inv1)
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self.connect_inst(["w_en_bar", "pre_w_en", "vdd", "gnd"])
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# BUFFER INVERTERS FOR W_EN
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self.pre_w_en_bar_inst = self.add_inst(name="inv_pre_w_en_bar",
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mod=self.inv2)
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self.connect_inst(["pre_w_en", "pre_w_en_bar", "vdd", "gnd"])
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self.w_en_inst = self.add_inst(name="inv_w_en2",
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mod=self.inv8)
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self.connect_inst(["pre_w_en_bar", "w_en", "vdd", "gnd"])
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# No we signal is needed for write-only ports
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input_name = "gated_clk"
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# BUFFER FOR W_EN
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self.w_en_inst = self.add_inst(name="w_en_buf",
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mod=self.pbuf8)
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self.connect_inst([input_name, "w_en", "vdd", "gnd"])
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def place_we_row(self,row):
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x_off = self.ctrl_dff_inst.width + self.internal_bus_width
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(y_off,mirror)=self.get_offset(row)
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w_en_bar_offset = vector(x_off, y_off)
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self.w_en_bar_inst.place(offset=w_en_bar_offset,
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mirror=mirror)
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if self.port_type == "rw":
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x_off += self.nand3.width
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else:
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pre_w_en_offset = vector(x_off, y_off)
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self.pre_w_en_inst.place(offset=pre_w_en_offset,
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mirror=mirror)
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x_off += self.nand2.width
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pre_w_en_offset = vector(x_off, y_off)
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self.pre_w_en_inst.place(offset=pre_w_en_offset,
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mirror=mirror)
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x_off += self.inv1.width
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pre_w_en_bar_offset = vector(x_off, y_off)
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self.pre_w_en_bar_inst.place(offset=pre_w_en_bar_offset,
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mirror=mirror)
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x_off += self.inv2.width
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w_en_offset = vector(x_off, y_off)
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w_en_offset = vector(x_off, y_off)
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self.w_en_inst.place(offset=w_en_offset,
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mirror=mirror)
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x_off += self.inv8.width
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self.row_end_inst.append(self.w_en_inst)
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@ -17,38 +17,40 @@ class pand2(design.design):
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unique_id = 1
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def __init__(self, driver_size=4, height=bitcell.height, name=""):
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stage_effort = 4
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# FIXME: Change the number of stages to support high drives.
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def __init__(self, size=1, height=bitcell.height, name=""):
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self.size = size
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self.height = height
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if name=="":
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name = "pand2_{0}_{1}".format(driver_size, pand2.unique_id)
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name = "pand2_{0}_{1}".format(size, pand2.unique_id)
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pand2.unique_id += 1
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def create_netlist(self):
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self.add_pins()
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self.create_modules()
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self.create_insts()
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def create_modules(self):
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# Shield the cap, but have at least a stage effort of 4
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self.nand = pnand2(height=height)
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self.nand = pnand2(height=self.height)
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self.add_mod(self.nand)
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self.inv = pinv(size=driver_size, height=height)
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self.inv = pinv(size=self.size, height=self.height)
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self.add_mod(self.inv)
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self.width = self.nand.width + self.inv.width
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self.height = self.inv.height
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self.create_layout()
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#self.offset_all_coordinates()
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self.DRC_LVS()
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def create_layout(self):
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self.add_pins()
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self.add_insts()
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self.width = self.nand.width + self.inv.width
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self.place_insts()
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self.add_wires()
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self.add_layout_pins()
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@ -59,20 +61,21 @@ class pand2(design.design):
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self.add_pin("vdd")
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self.add_pin("gnd")
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def add_insts(self):
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# Add NAND to the right
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def create_insts(self):
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self.nand_inst=self.add_inst(name="pand2_nand",
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mod=self.nand,
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offset=vector(0,0))
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mod=self.nand)
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self.connect_inst(["A", "B", "zb_int", "vdd", "gnd"])
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self.inv_inst=self.add_inst(name="pand2_inv",
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mod=self.inv)
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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def place_insts(self):
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# Add NAND to the right
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self.nand_inst.place(offset=vector(0,0))
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# Add INV to the right
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self.inv_inst=self.add_inst(name="pand2_inv",
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mod=self.inv,
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offset=vector(self.nand_inst.rx(),0))
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self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
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self.inv_inst.place(offset=vector(self.nand_inst.rx(),0))
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def add_wires(self):
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# nand Z to inv A
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@ -16,39 +16,33 @@ class pbuf(design.design):
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unique_id = 1
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def __init__(self, driver_size=4, height=bitcell.height, name=""):
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def __init__(self, size=4, height=bitcell.height, name=""):
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stage_effort = 4
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self.stage_effort = 4
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self.size = size
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self.width = 0
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self.height = height
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# FIXME: Change the number of stages to support high drives.
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if name=="":
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name = "pbuf_{0}_{1}".format(driver_size, pbuf.unique_id)
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name = "pbuf_{0}_{1}".format(self.size, pbuf.unique_id)
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pbuf.unique_id += 1
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design.design.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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# Shield the cap, but have at least a stage effort of 4
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input_size = max(1,int(driver_size/stage_effort))
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self.inv1 = pinv(size=input_size, height=height) # 1
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self.add_mod(self.inv1)
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self.inv2 = pinv(size=driver_size, height=height) # 2
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self.add_mod(self.inv2)
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self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
|
||||
self.width = self.inv1.width + self.inv2.width
|
||||
self.height = self.inv1.height
|
||||
|
||||
self.create_layout()
|
||||
|
||||
#self.offset_all_coordinates()
|
||||
|
||||
self.DRC_LVS()
|
||||
def create_netlist(self):
|
||||
self.add_pins()
|
||||
self.create_modules()
|
||||
self.create_insts()
|
||||
|
||||
def create_layout(self):
|
||||
self.add_pins()
|
||||
self.add_insts()
|
||||
self.width = self.inv1.width + self.inv2.width
|
||||
self.place_insts()
|
||||
self.add_wires()
|
||||
self.add_layout_pins()
|
||||
|
||||
|
|
@ -58,19 +52,31 @@ class pbuf(design.design):
|
|||
self.add_pin("vdd")
|
||||
self.add_pin("gnd")
|
||||
|
||||
def add_insts(self):
|
||||
# Add INV1 to the right
|
||||
def create_modules(self):
|
||||
# Shield the cap, but have at least a stage effort of 4
|
||||
input_size = max(1,int(self.size/self.stage_effort))
|
||||
self.inv1 = pinv(size=input_size, height=self.height)
|
||||
self.add_mod(self.inv1)
|
||||
|
||||
self.inv2 = pinv(size=self.size, height=self.height)
|
||||
self.add_mod(self.inv2)
|
||||
|
||||
def create_insts(self):
|
||||
self.inv1_inst=self.add_inst(name="buf_inv1",
|
||||
mod=self.inv1,
|
||||
offset=vector(0,0))
|
||||
mod=self.inv1)
|
||||
self.connect_inst(["A", "zb_int", "vdd", "gnd"])
|
||||
|
||||
|
||||
# Add INV2 to the right
|
||||
self.inv2_inst=self.add_inst(name="buf_inv2",
|
||||
mod=self.inv2,
|
||||
offset=vector(self.inv1_inst.rx(),0))
|
||||
mod=self.inv2)
|
||||
self.connect_inst(["zb_int", "Z", "vdd", "gnd"])
|
||||
|
||||
def place_insts(self):
|
||||
# Add INV1 to the right
|
||||
self.inv1_inst.place(vector(0,0))
|
||||
|
||||
# Add INV2 to the right
|
||||
self.inv2_inst.place(vector(self.inv1_inst.rx(),0))
|
||||
|
||||
|
||||
def add_wires(self):
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@ class pnand2(pgate.pgate):
|
|||
self.create_netlist()
|
||||
if not OPTS.netlist_only:
|
||||
self.create_layout()
|
||||
#self.DRC_LVS()
|
||||
|
||||
|
||||
def create_netlist(self):
|
||||
|
|
|
|||
Loading…
Reference in New Issue