mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed delay test values.
This commit is contained in:
Hunter Nichols
parent
722bc907c4
commit
0c3c58011b
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@ -569,6 +569,7 @@ class delay(simulation):
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#Update target
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target_period = 0.5 * (ub_period + lb_period)
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#key=input("press return to continue")
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def try_period(self, feasible_delays):
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@ -590,7 +591,7 @@ class delay(simulation):
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#Delays/slews based on the period will cause the min_period search to come to the wrong period.
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if self.sram.col_addr_size>0 and "slew" in dname:
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continue
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if not relative_compare(results[port][dname],feasible_delays[port][dname],error_tolerance=0.05):
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debug.info(2,"Delay too big {0} vs {1}".format(results[port][dname],feasible_delays[port][dname]))
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return False
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@ -244,9 +244,10 @@ class stimuli():
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reltol = 0.005 # 0.5%
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else:
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reltol = 0.001 # 0.1%
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timestep = 10 #ps, was 5ps but ngspice was complaining the timestep was too small in certain tests.
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# UIC is needed for ngspice to converge
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self.sf.write(".TRAN 5p {0}n UIC\n".format(end_time))
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self.sf.write(".TRAN {0}p {1}n UIC\n".format(timestep,end_time))
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if OPTS.spice_name == "ngspice":
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# ngspice sometimes has convergence problems if not using gear method
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# which is more accurate, but slower than the default trapezoid method
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@ -50,27 +50,27 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.15801],
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'delay_lh': [0.15801],
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'leakage_power': 0.0023949,
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'min_period': 0.41,
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'read0_power': [0.628],
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'read1_power': [0.60328],
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'slew_hl': [0.092516],
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'slew_lh': [0.092516],
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'write0_power': [0.7510600000000001],
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'write1_power': [0.66619]}
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golden_data = {'delay_hl': [0.2011],
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'delay_lh': [0.2011],
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'leakage_power': 0.0014218000000000002,
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'min_period': 0.41,
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'read0_power': [0.63604],
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'read1_power': [0.6120599999999999],
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'slew_hl': [0.10853],
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'slew_lh': [0.10853],
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'write0_power': [0.51742],
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'write1_power': [0.51095]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.2],
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'delay_lh': [1.2],
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'leakage_power': 0.026912,
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'min_period': 2.891,
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'read0_power': [24.7996],
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'read1_power': [23.9464],
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'slew_hl': [0.7045815],
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'slew_lh': [0.7045815],
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'write0_power': [27.8985],
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'write1_power': [25.1812]}
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golden_data = {'delay_hl': [1.3911],
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'delay_lh': [1.3911],
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'leakage_power': 0.0278488,
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'min_period': 2.812,
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'read0_power': [22.1183],
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'read1_power': [21.4388],
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'slew_hl': [0.7397553],
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'slew_lh': [0.7397553],
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'write0_power': [19.4103],
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'write1_power': [20.1167]}
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else:
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self.assertTrue(False) # other techs fail
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# Check if no too many or too few results
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@ -50,27 +50,27 @@ class timing_sram_test(openram_test):
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data.update(port_data[0])
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if OPTS.tech_name == "freepdk45":
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golden_data = {'delay_hl': [0.1587689],
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'delay_lh': [0.1587689],
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'leakage_power': 0.02824871,
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'min_period': 0.43,
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'read0_power': [0.5932789],
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'read1_power': [0.5733669],
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'slew_hl': [0.09096027999999999],
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'slew_lh': [0.09096027999999999],
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'write0_power': [0.7133274],
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'write1_power': [0.6390777]}
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golden_data = {'delay_hl': [0.20443139999999999],
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'delay_lh': [0.20443139999999999],
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'leakage_power': 0.0017840640000000001,
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'min_period': 0.41,
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'read0_power': [0.6435831],
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'read1_power': [0.6233463],
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'slew_hl': [0.1138734],
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'slew_lh': [0.1138734],
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'write0_power': [0.5205761],
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'write1_power': [0.5213689]}
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elif OPTS.tech_name == "scn4m_subm":
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golden_data = {'delay_hl': [1.342843],
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'delay_lh': [1.342843],
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'leakage_power': 0.001683033,
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'min_period': 3.906,
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'read0_power': [19.55096],
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'read1_power': [18.99015],
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'slew_hl': [0.7687596],
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'slew_lh': [0.7687596],
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'write0_power': [22.285880000000002],
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'write1_power': [19.97167]}
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golden_data = {'delay_hl': [1.610911],
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'delay_lh': [1.610911],
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'leakage_power': 0.0023593859999999998,
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'min_period': 3.281,
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'read0_power': [20.763569999999998],
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'read1_power': [20.32745],
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'slew_hl': [0.7986348999999999],
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'slew_lh': [0.7986348999999999],
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'write0_power': [17.58272],
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'write1_power': [18.523419999999998]}
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else:
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self.assertTrue(False) # other techs fail
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