mirror of https://github.com/VLSIDA/OpenRAM.git
Expand grids to maximal pin before removing blockages
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parent
389bb91af4
commit
7fce6f06ca
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@ -608,7 +608,7 @@ class pin_group:
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for pin_list in self.pins:
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for pin in pin_list:
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debug.info(2," Converting {0}".format(pin))
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debug.warning(" Expanding conversion {0}".format(pin))
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# Determine which tracks the pin overlaps
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pin_in_tracks=self.router.convert_pin_to_tracks(self.name, pin, expansion=1)
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pin_set.update(pin_in_tracks)
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@ -618,7 +618,7 @@ class pin_group:
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self.router.write_debug_gds("blocked_pin.gds")
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# We need to route each of the components, so don't combine the groups
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self.grids = pin_set | blockage_set
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self.grids = pin_set
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# Remember the secondary grids for removing adjacent pins in wide metal spacing
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self.secondary_grids = blockage_set - pin_set
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@ -182,10 +182,10 @@ class router(router_tech):
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#print_time("Combine pins",datetime.now(), start_time)
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#self.write_debug_gds("debug_combine_pins.gds",stop_program=True)
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# Separate any adjacent grids of differing net names to prevent wide metal DRC violations
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# Separate any adjacent grids of differing net names that overlap
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# Must be done before enclosing pins
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#start_time = datetime.now()
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#self.separate_adjacent_pins(self.supply_rail_space_width)
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self.separate_adjacent_pins(0)
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#print_time("Separate pins",datetime.now(), start_time)
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# For debug
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#self.separate_adjacent_pins(1)
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@ -515,7 +515,7 @@ class router(router_tech):
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# scale the size bigger to include neaby tracks
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ll=ll.scale(self.track_factor).floor()
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ur=ur.scale(self.track_factor).ceil()
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#print(pin)
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# Keep tabs on tracks with sufficient and insufficient overlap
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sufficient_list = set()
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insufficient_list = set()
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@ -528,23 +528,26 @@ class router(router_tech):
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sufficient_list.update([full_overlap])
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if partial_overlap:
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insufficient_list.update([partial_overlap])
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debug.info(3,"Converting [ {0} , {1} ] full={2} partial={3}".format(x,y, full_overlap, partial_overlap))
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debug.info(2,"Converting [ {0} , {1} ] full={2} partial={3}".format(x,y, full_overlap, partial_overlap))
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# Remove the blocked grids
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sufficient_list.difference_update(self.blocked_grids)
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insufficient_list.difference_update(self.blocked_grids)
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# Return all grids with any potential overlap (sufficient or not)
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return sufficient_list|insufficient_list
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# # Remove the blocked grids
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# sufficient_list.difference_update(self.blocked_grids)
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# insufficient_list.difference_update(self.blocked_grids)
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if len(sufficient_list)>0:
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return sufficient_list
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elif expansion==0 and len(insufficient_list)>0:
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best_pin = self.get_all_offgrid_pin(pin, insufficient_list)
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#print(best_pin)
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return best_pin
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elif expansion>0:
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nearest_pin = self.get_furthest_offgrid_pin(pin, insufficient_list)
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return nearest_pin
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else:
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return set()
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# if len(sufficient_list)>0:
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# return sufficient_list
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# elif expansion==0 and len(insufficient_list)>0:
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# best_pin = self.get_all_offgrid_pin(pin, insufficient_list)
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# #print(best_pin)
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# return best_pin
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# elif expansion>0:
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# nearest_pin = self.get_furthest_offgrid_pin(pin, insufficient_list)
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# return nearest_pin
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# else:
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# return set()
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def get_all_offgrid_pin(self, pin, insufficient_list):
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"""
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@ -71,7 +71,7 @@ class supply_router(router):
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#start_time = datetime.now()
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self.find_pins_and_blockages([self.vdd_name, self.gnd_name])
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#print_time("Pins and blockages",datetime.now(), start_time)
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self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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#self.write_debug_gds("pin_enclosures.gds",stop_program=True)
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# Add the supply rails in a mesh network and connect H/V with vias
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#start_time = datetime.now()
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