mirror of https://github.com/VLSIDA/OpenRAM.git
Add non-minimum width metal2 in route when vias can be close
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@ -10,6 +10,7 @@ from globals import OPTS, print_time
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from sram_base import sram_base
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from bank import bank
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from contact import m2m3
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from dff_buf_array import dff_buf_array
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from dff_array import dff_array
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@ -216,6 +217,9 @@ class sram_1bank(sram_base):
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data_dff_clk_pin = self.data_dff_insts[port].get_pin("clk")
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data_dff_clk_pos = data_dff_clk_pin.center()
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mid_pos = vector(clk_steiner_pos.x, data_dff_clk_pos.y)
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# In some designs, the steiner via will be too close to the mid_pos via
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# so make the wire as wide as the contacts
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self.add_path("metal2",[mid_pos, clk_steiner_pos], width=max(m2m3.width,m2m3.height))
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self.add_wire(("metal3","via2","metal2"),[data_dff_clk_pos, mid_pos, clk_steiner_pos])
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