Add size commments to spize. Change pdriver stage effort.

compiler/base/hierarchy_spice.py

@@ -19,13 +19,15 @@ class spice():
         # Holds subckts/mods for this module
         self.mods = []  
         # Holds the pins for this module
-        self.pins = []  
+        self.pins = []
         # The type map of each pin: INPUT, OUTPUT, INOUT, POWER, GROUND
         # for each instance, this is the set of nets/nodes that map to the pins for this instance
         self.pin_type = {} 
         # THE CONNECTIONS MUST MATCH THE ORDER OF THE PINS (restriction imposed by the
         # Spice format)
         self.conns = []
+        # Keep track of any comments to add the the spice
+        self.comments = []
 
         self.sp_read()
 
@@ -33,6 +35,10 @@ class spice():
 # Spice circuit
 ############################################################
 
+    def add_comment(self, comment):
+        """ Add a comment to the spice file """
+        self.comments.append(comment)
+        
     def add_pin(self, name, pin_type="INOUT"):
         """ Adds a pin to the pins list. Default type is INOUT signal. """
         self.pins.append(name)
@@ -162,6 +168,9 @@ class spice():
             sp.write("\n.SUBCKT {0} {1}\n".format(self.name,
                                                   " ".join(self.pins)))
 
+            for line in self.comments:
+                sp.write("* {}\n".format(line))
+                    
             # every instance must have a set of connections, even if it is empty.
             if  len(self.insts)!=len(self.conns):
                 debug.error("{0} : Not all instance pins ({1}) are connected ({2}).".format(self.name,

compiler/modules/control_logic.py

@@ -86,8 +86,7 @@ class control_logic(design.design):
         
         # Special gates: inverters for buffering
         # clk_buf drives a flop for every address and control bit
-        clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2) + self.num_control_signals
-        #clock_fanout = max(1,int(self.num_rows/4))
+        clock_fanout = math.log(self.num_words,2) + math.log(self.words_per_row,2)+1 + self.num_control_signals
         self.clkbuf = factory.create(module_type="pdriver",
                                      fanout=clock_fanout,
                                      height=dff_height)

compiler/pgates/pand2.py

@@ -15,7 +15,7 @@ class pand2(pgate.pgate):
         
         pgate.pgate.__init__(self, name, height)
         debug.info(1, "Creating {}".format(self.name))
-
+        self.add_comment("size: {}".format(size))
         
         self.create_netlist()
         if not OPTS.netlist_only:        

compiler/pgates/pbuf.py

@@ -18,7 +18,8 @@ class pbuf(pgate.pgate):
 
         pgate.pgate.__init__(self, name, height)
         debug.info(1, "creating {0} with size of {1}".format(self.name,self.size))
-
+        self.add_comment("size: {}".format(size))
+        
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()

compiler/pgates/pdriver.py

@@ -13,7 +13,7 @@ class pdriver(pgate.pgate):
     """
     def __init__(self, name, neg_polarity=False, fanout=0, size_list=None, height=None):
 
-        self.stage_effort = 4
+        self.stage_effort = 3
         self.height = height 
         self.neg_polarity = neg_polarity
         self.size_list = size_list
@@ -27,6 +27,8 @@ class pdriver(pgate.pgate):
         
         self.compute_sizes()
 
+        self.add_comment("sizes: {}".format(str(self.size_list)))
+        
         self.create_netlist()
         if not OPTS.netlist_only:
             self.create_layout()

compiler/pgates/pinv.py

@@ -26,6 +26,7 @@ class pinv(pgate.pgate):
         # have poly connected, for example.
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pinv structure {0} with size of {1}".format(name, size))
+        self.add_comment("size: {}".format(size))
         
         self.size = size
         self.nmos_size = size

compiler/pgates/pinvbuf.py

@@ -25,6 +25,7 @@ class pinvbuf(design.design):
 
         design.design.__init__(self, name) 
         debug.info(1, "Creating {}".format(self.name))
+        self.add_comment("size: {}".format(size))
 
         self.create_netlist()
         if not OPTS.netlist_only:

compiler/pgates/pnand2.py

@@ -16,6 +16,7 @@ class pnand2(pgate.pgate):
         """ Creates a cell for a simple 2 input nand """
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pnand2 structure {0} with size of {1}".format(name, size))
+        self.add_comment("size: {}".format(size))
 
         self.size = size
         self.nmos_size = 2*size

compiler/pgates/pnand3.py

@@ -15,6 +15,7 @@ class pnand3(pgate.pgate):
         """ Creates a cell for a simple 3 input nand """
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pnand3 structure {0} with size of {1}".format(name, size))
+        self.add_comment("size: {}".format(size))
 
         # We have trouble pitch matching a 3x sizes to the bitcell...
         # If we relax this, we could size this better.

compiler/pgates/pnor2.py

@@ -15,6 +15,7 @@ class pnor2(pgate.pgate):
         """ Creates a cell for a simple 2 input nor """
         pgate.pgate.__init__(self, name, height)
         debug.info(2, "create pnor2 structure {0} with size of {1}".format(name, size))
+        self.add_comment("size: {}".format(size))
 
         self.nmos_size = size
         # We will just make this 1.5 times for now. NORs are not ideal anyhow.