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Missing gap in port 1 col decoder

This commit is contained in:
Matt Guthaus 2018-11-28 18:07:31 -08:00
parent d041a498f3
commit 02a67f9867
1 changed files with 1 additions and 1 deletions
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2
compiler/modules/bank.py
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@ -295,7 +295,7 @@ class bank(design.design):
# Above the bitcell array with a well spacing
x_offset = self.bitcell_array.width + self.central_bus_width[port] + self.wordline_driver.width + 0.5*self.row_decoder.width
if self.col_addr_size > 0:
y_offset = self.bitcell_array.height + self.column_decoder.height
y_offset = self.bitcell_array.height + self.column_decoder.height + self.m2_gap
else:
y_offset = self.bitcell_array.height
y_offset += 2*drc("well_to_well")