Added option to use delay chain size defined in tech.py

compiler/modules/control_logic.py

@@ -109,24 +109,41 @@ class control_logic(design.design):
             from importlib import reload
             c = reload(__import__(OPTS.replica_bitline))
             replica_bitline = getattr(c, OPTS.replica_bitline)
-            
-            delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
             bitcell_loads = int(math.ceil(self.num_rows * parameter["rbl_height_percentage"]))
-            self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, bitcell_loads, name="replica_bitline_"+self.port_type)
-            
-            if self.sram != None:
-                self.set_sen_wl_delays()
-            
-            if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
-                #This resizes to match fall and rise delays, can make the delay chain weird sizes.
-                # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
-                # self.replica_bitline = replica_bitline(stage_list, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
+            if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
+                delay_stages =  parameter["static_delay_stages"]
+                delay_fanout = parameter["static_fanout_per_stage"]
+                debug.info(1, "Using tech parameters to size delay chain: stages={}, fanout={}".format(delay_stages,delay_fanout))
+                self.replica_bitline = replica_bitline([delay_fanout]*delay_stages,
+                                                        bitcell_loads, 
+                                                        name="replica_bitline_"+self.port_type)
                 
-                #This resizes based on total delay. 
-                delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
-                self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, bitcell_loads, name="replica_bitline_resized_"+self.port_type)
+            else: #Otherwise, use a heuristic and/or model based sizing.
+                #First use a heuristic
+                delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
+                self.replica_bitline = replica_bitline([delay_fanout_heuristic]*delay_stages_heuristic, 
+                                                        bitcell_loads,
+                                                        name="replica_bitline_"+self.port_type)
                 
-                self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
+                #Use a model to determine the delays with that heuristic
+                if self.sram != None:
+                    self.set_sen_wl_delays()
+               
+                #Resize if necessary
+                if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_total_timing_match(): #check condition based on resizing method
+                    #This resizes to match fall and rise delays, can make the delay chain weird sizes.
+                    # stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
+                    # self.replica_bitline = replica_bitline(stage_list, 
+                                                             # bitcell_loads, 
+                                                             # name="replica_bitline_resized_"+self.port_type)
+                    
+                    #This resizes based on total delay. 
+                    delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
+                    self.replica_bitline = replica_bitline([delay_fanout]*delay_stages, 
+                                                           bitcell_loads, 
+                                                           name="replica_bitline_resized_"+self.port_type)
+                    
+                    self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
                 
             self.add_mod(self.replica_bitline)
 

compiler/options.py

@@ -71,6 +71,9 @@ class options(optparse.Values):
     # You can manually specify banks, but it is better to auto-detect it.
     num_banks = 1
     
+    #Uses the delay chain size in the tech.py file rather automatic sizing.
+    use_tech_delay_chain_size = False
+    
     # These are the default modules that can be over-riden
     decoder = "hierarchical_decoder"
     dff_array = "dff_array"

technology/freepdk45/tech/tech.py

@@ -329,12 +329,15 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Parameters related to sense amp enable timing and delay chain/RBL sizing
+parameter["static_delay_stages"] = 4
+parameter["static_fanout_per_stage"] = 3
 parameter["dff_clk_cin"] = 30.6             #relative capacitance
 parameter["6tcell_wl_cin"] = 3              #relative capacitance
 parameter["min_inv_para_delay"] = .5        #Tau delay units
 parameter["sa_en_pmos_size"] = .72          #micro-meters
 parameter["sa_en_nmos_size"] = .27          #micro-meters
 parameter["rbl_height_percentage"] = .5     #Height of RBL compared to bitcell array 
+
 ###################################################
 ##END Spice Simulation Parameters
 ###################################################

technology/scn4m_subm/tech/tech.py

@@ -295,6 +295,8 @@ spice["nand3_transition_prob"] = .1094    # Transition probability of 3-input na
 spice["nor2_transition_prob"] = .1875     # Transition probability of 2-input nor.
 
 #Logical Effort relative values for the Handmade cells
+parameter["static_delay_stages"] = 4
+parameter["static_fanout_per_stage"] = 3
 parameter["dff_clk_cin"] = 27.5
 parameter["6tcell_wl_cin"] = 2
 parameter["min_inv_para_delay"] = .5