mirror of https://github.com/VLSIDA/OpenRAM.git
Control logic passes DRC/LVS in SCMOS
This commit is contained in:
Matt Guthaus
parent
410115e830
commit
93904d9f2d
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@ -8,8 +8,8 @@ from pbuf import pbuf
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from pand2 import pand2
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from pnand2 import pnand2
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from pinvbuf import pinvbuf
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from dff_inv import dff_inv
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from dff_inv_array import dff_inv_array
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from dff_buf import dff_buf
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from dff_buf_array import dff_buf_array
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import math
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from vector import vector
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from globals import OPTS
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@ -64,10 +64,10 @@ class control_logic(design.design):
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def add_modules(self):
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""" Add all the required modules """
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dff = dff_inv()
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dff = dff_buf()
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dff_height = dff.height
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self.ctrl_dff_array = dff_inv_array(rows=self.num_control_signals,columns=1)
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self.ctrl_dff_array = dff_buf_array(rows=self.num_control_signals,columns=1)
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self.add_mod(self.ctrl_dff_array)
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self.and2 = pand2(size=4,height=dff_height)
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@ -135,9 +135,11 @@ class control_logic(design.design):
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# list of output control signals (for making a vertical bus)
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if self.port_type == "rw":
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self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "we", "we_bar", "cs"]
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "we", "clk_buf", "we_bar", "cs"]
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elif self.port_type == "r":
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs_bar", "cs"]
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else:
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self.internal_bus_list = ["clk_buf", "gated_clk_bar", "gated_clk_buf", "cs"]
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self.internal_bus_list = ["gated_clk_bar", "gated_clk_buf", "clk_buf", "cs"]
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# leave space for the bus plus one extra space
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self.internal_bus_width = (len(self.internal_bus_list)+1)*self.m2_pitch
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@ -248,7 +250,7 @@ class control_logic(design.design):
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""" Create the replica bitline """
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self.rbl_inst=self.add_inst(name="replica_bitline",
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mod=self.replica_bitline)
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self.connect_inst(["pre_p_en", "pre_s_en", "vdd", "gnd"])
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self.connect_inst(["rbl_in", "pre_s_en", "vdd", "gnd"])
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def place_rbl(self,row):
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""" Place the replica bitline """
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@ -313,24 +315,24 @@ class control_logic(design.design):
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self.row_end_inst.append(self.gated_clk_bar_inst)
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def route_gated_clk_bar(self):
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clkbuf_map = zip(["A"], ["clk_buf"])
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self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets)
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out_pos = self.clk_bar_inst.get_pin("Z").center()
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in_pos = self.gated_clk_bar_inst.get_pin("B").center()
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mid1 = vector(in_pos.x,out_pos.y)
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self.add_wire(("metal1","via1","metal2"),[out_pos, mid1, in_pos])
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clkbuf_map = zip(["A"], ["cs"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets)
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
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clkbuf_map = zip(["A"], ["clk_buf"])
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self.connect_vertical_bus(clkbuf_map, self.clk_bar_inst, self.rail_offsets)
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clkbuf_map = zip(["Z"], ["gated_clk_bar"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_bar_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
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def create_gated_clk_buf_row(self):
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self.gated_clk_buf_inst = self.add_inst(name="gated_clkinv",
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mod=self.and2)
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self.connect_inst(["cs","clk_buf","gated_clk_buf","vdd","gnd"])
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self.connect_inst(["clk_buf", "cs","gated_clk_buf","vdd","gnd"])
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def place_gated_clk_buf_row(self,row):
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""" Place the gated clk logic below the control flops """
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@ -343,7 +345,7 @@ class control_logic(design.design):
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self.row_end_inst.append(self.gated_clk_buf_inst)
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def route_gated_clk_buf(self):
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clkbuf_map = zip(["A", "B"], ["clk_buf", "we_bar"])
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clkbuf_map = zip(["A", "B"], ["clk_buf", "cs"])
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self.connect_vertical_bus(clkbuf_map, self.gated_clk_buf_inst, self.rail_offsets)
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@ -371,10 +373,16 @@ class control_logic(design.design):
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self.connect_output(self.wl_en_inst, "Z", "wl_en")
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def create_rbl_in_row(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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input_name = "cs_bar"
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# input: gated_clk_bar, we_bar, output: rbl_in
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self.rbl_in_inst=self.add_inst(name="and2_rbl_in",
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mod=self.and2)
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self.connect_inst(["gated_clk_bar", "we_bar", "rbl_in", "vdd", "gnd"])
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self.connect_inst(["gated_clk_bar", input_name, "rbl_in", "vdd", "gnd"])
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def place_rbl_in_row(self,row):
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x_off = self.control_x_offset
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@ -388,8 +396,13 @@ class control_logic(design.design):
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def route_rbl_in(self):
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""" Connect the logic for the rbl_in generation """
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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input_name = "cs_bar"
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# Connect the NAND gate inputs to the bus
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rbl_in_map = zip(["A", "B"], ["gated_clk_bar", "we_bar"])
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rbl_in_map = zip(["A", "B"], ["gated_clk_bar", input_name])
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self.connect_vertical_bus(rbl_in_map, self.rbl_in_inst, self.rail_offsets)
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# Connect the output of the precharge enable to the RBL input
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@ -405,10 +418,16 @@ class control_logic(design.design):
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rotate=90)
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def create_pen_row(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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# No we for read-only reports, so use cs
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input_name = "cs_bar"
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# input: gated_clk_bar, we_bar, output: pre_p_en
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self.pre_p_en_inst=self.add_inst(name="and2_pre_p_en",
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mod=self.and2)
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self.connect_inst(["gated_clk_buf", "we_bar", "pre_p_en", "vdd", "gnd"])
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self.connect_inst(["gated_clk_buf", input_name, "pre_p_en", "vdd", "gnd"])
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# input: pre_p_en, output: p_en_bar
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self.p_en_bar_inst=self.add_inst(name="inv_p_en_bar",
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@ -431,8 +450,14 @@ class control_logic(design.design):
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self.row_end_inst.append(self.pre_p_en_inst)
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def route_pen(self):
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if self.port_type == "rw":
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input_name = "we_bar"
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else:
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# No we for read-only reports, so use cs
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input_name = "cs_bar"
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# Connect the NAND gate inputs to the bus
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pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", "we_bar"])
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pre_p_en_in_map = zip(["A", "B"], ["gated_clk_buf", input_name])
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self.connect_vertical_bus(pre_p_en_in_map, self.pre_p_en_inst, self.rail_offsets)
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out_pos = self.pre_p_en_inst.get_pin("Z").center()
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@ -502,6 +527,7 @@ class control_logic(design.design):
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if self.port_type == "rw":
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input_name = "we"
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else:
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# No we for write-only reports, so use cs
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input_name = "cs"
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wen_map = zip(["A"], [input_name])
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@ -510,24 +536,21 @@ class control_logic(design.design):
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self.connect_output(self.w_en_inst, "Z", "w_en")
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def create_dffs(self):
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""" Add the three input DFFs (with inverters) """
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self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs",
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mod=self.ctrl_dff_array)
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self.connect_inst(self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list)
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def place_dffs(self):
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""" Place the input DFFs (with inverters) """
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self.ctrl_dff_inst.place(vector(0,0))
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def route_dffs(self):
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""" Route the input inverters """
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if self.port_type == "r":
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control_inputs = ["cs"]
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if self.port_type == "rw":
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dff_out_map = zip(["dout_bar_0", "dout_bar_1", "dout_1"], ["cs", "we", "we_bar"])
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elif self.port_type == "r":
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dff_out_map = zip(["dout_bar_0", "dout_0"], ["cs", "cs_bar"])
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else:
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control_inputs = ["cs", "we"]
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dff_out_map = zip(["dout_bar_{}".format(i) for i in range(2*self.num_control_signals - 1)], control_inputs)
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets)
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dff_out_map = zip(["dout_bar_0"], ["cs"])
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self.connect_vertical_bus(dff_out_map, self.ctrl_dff_inst, self.rail_offsets, ("metal3", "via2", "metal2"))
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# Connect the clock rail to the other clock rail
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in_pos = self.ctrl_dff_inst.get_pin("clk").uc()
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