mirror of https://github.com/VLSIDA/OpenRAM.git
Updated naming, added compute_sizes(), and fixed sizing function.
This commit is contained in:
Jennifer Eve Sowash
parent
2534a32e20
commit
5e19cf1e24
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@ -1,5 +1,5 @@
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import debug
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import design
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import pgate
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import math
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from tech import drc
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from math import log
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@ -7,7 +7,7 @@ from vector import vector
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from globals import OPTS
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from pinv import pinv
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class pdriver(design.design):
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class pdriver(pgate.pgate):
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"""
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This instantiates an even or odd number of inverters sized for driving a load.
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"""
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@ -15,62 +15,59 @@ class pdriver(design.design):
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inv_list = []
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inv_inst_list = []
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def __init__(self, driver_size=4, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
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def __init__(self, height=None, name="", neg_polarity=False, c_load=8, size_list = []):
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self.stage_effort = 4
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self.row_height = height
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# FIXME: Change the number of stages to support high drives.
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# stage effort of 4 or less
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self.driver_size = driver_size
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self.row_height = height
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self.neg_polarity = neg_polarity
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self.size_list = size_list
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self.c_load = c_load
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if len(self.size_list) > 0 and (self.c_load != 8 or self.neg_polarity):
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raise Exception("Cannot specify both size_list and neg_polarity or c_load.")
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# size_list specified
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if len(self.size_list) > 0:
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if not len(self.size_list) % 2:
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neg_polarity = True
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self.inv_num = len(self.size_list)
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else:
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# with pinv = i
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rho = 3.59
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N = max(1, int(math.log1p(self.stage_effort)/math.log1p(rho)))
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if self.neg_polarity:
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if (N % 2 == 0): # if N is even
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self.inv_num = int(N)+1
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else: # if N is odd
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self.inv_num = int(N)
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else: # positive polarity
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if (N % 2 == 0):
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self.inv_num = int(N)
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else:
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self.inv_num = int(N)+1
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self.compute_sizes()
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if name=="":
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name = "pdriver_{0}_{1}_{2}".format(self.driver_size, self.inv_num,
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name = "pdriver_{0}_{1}_{2}".format(self.stage_effort, self.num_inv,
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pdriver.unique_id)
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pdriver.unique_id += 1
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design.design.__init__(self, name)
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pgate.pgate.__init__(self, name)
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debug.info(1, "Creating {}".format(self.name))
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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def compute_sizes(self):
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# size_list specified
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if len(self.size_list) > 0:
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if not len(self.size_list) % 2:
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neg_polarity = True
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self.num_inv = len(self.size_list)
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else:
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# rho with p_inv = 1
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rho = 3.59
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num_stages = max(1, int(math.log1p(self.stage_effort)/math.log1p(rho)))
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if self.neg_polarity:
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if (num_stages % 2 == 0): # if num_stages is even
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self.num_inv = int(num_stages)+1
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else: # if num_stages is odd
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self.num_inv = int(num_stages)
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else: # positive polarity
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if (num_stages % 2 == 0):
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self.num_inv = int(num_stages)
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else:
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self.num_inv = int(num_stages)+1
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def create_netlist(self):
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self.add_pins()
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self.add_modules()
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self.create_insts()
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def create_layout(self):
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self.width = self.inv_num * self.inv_list[0].width
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self.width = self.num_inv * self.inv_list[0].width
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self.height = self.inv_list[0].height
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self.place_modules()
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@ -91,31 +88,27 @@ class pdriver(design.design):
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self.inv_list.append(pinv(size=self.size_list[x], height=self.row_height))
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self.add_mod(self.inv_list[x])
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else: # find inv sizes
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# shield the cap, but have at least a stage effort of 4
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input_size = max(1,int(self.driver_size/self.stage_effort))
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self.inv_list.append(pinv(size=input_size, height=self.row_height))
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self.add_mod(self.inv_list[0])
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# work backwards
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for x in range(self.inv_num-1, 0, -1):
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c_in = max(input_size, int(round(self.c_load/self.stage_effort ,0)))
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# work backwards to find the size of each stage
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for x in range(self.num_inv-1, -1, -1):
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c_in = max(1, int(round(self.c_load/self.stage_effort,0)))
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self.c_load = c_in
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self.inv_list.append(pinv(size=c_in, height=self.row_height))
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self.add_mod(self.inv_list[x])
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def create_insts(self):
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for x in range(1,self.inv_num+1):
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for x in range(1,self.num_inv+1):
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# Create first inverter
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if x == 1:
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zbx_int = "Zb{}_int".format(x);
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self.inv_inst_list.append(self.add_inst(name="buf_inv{}".format(x),
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mod=self.inv_list[x-1]))
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if self.inv_num == 1:
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if self.num_inv == 1:
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self.connect_inst(["A", "Z", "vdd", "gnd"])
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else:
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self.connect_inst(["A", zbx_int, "vdd", "gnd"])
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# Create last inverter
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elif x == self.inv_num:
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elif x == self.num_inv:
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zbn_int = "Zb{}_int".format(x-1);
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self.inv_inst_list.append(self.add_inst(name="buf_inv{}".format(x),
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mod=self.inv_list[x-1]))
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@ -182,7 +175,7 @@ class pdriver(design.design):
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height = a_pin.height())
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def analytical_delay(self, slew, load=0.0):
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"""Calculate the analytical delay of DFF -> INV -> ... -> INV"""
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"""Calculate the analytical delay of INV1 -> ... -> INVn"""
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delay = 0;
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if len(self.inv_inst_list) == 1:
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delay = self.inv_inst_list[x].analytical_delay(slew=slew);
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@ -21,11 +21,19 @@ class pdriver_test(openram_test):
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import pdriver
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debug.info(2, "Testing inverter/buffer 4x 8x")
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# a tests the error message for specifying conflicting conditions
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#a = pdriver.pdriver(c_load = 4,size_list = [1,2,4,8])
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#a = pdriver.pdriver(size_list = [1,2,4,8])
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a = pdriver.pdriver(c_load = 4)
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#a = pdriver.pdriver(c_load = 4, neg_polarity = True)
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self.local_check(a)
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b = pdriver.pdriver(size_list = [1,2,4,8])
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c = pdriver.pdriver(c_load = 4)
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d = pdriver.pdriver(c_load = 4, neg_polarity = True)
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e = pdriver.pdriver(c_load = 64)
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f = pdriver.pdriver(c_load = 64, neg_polarity = False)
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#self.local_check(a)
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self.local_check(b)
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self.local_check(c)
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self.local_check(d)
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self.local_check(e)
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self.local_check(f)
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globals.end_openram()
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