mirror of https://github.com/VLSIDA/OpenRAM.git
Add the factory class
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import debug
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from globals import OPTS
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from importlib import reload
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class sram_factory:
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"""
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This is a factory pattern to create modules for usage in an SRAM.
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Since GDSII has a flat namespace, it requires modules to have unique
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names if their layout differs. This module ensures that any module
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with different layouts will have different names. It also ensures that
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identical layouts will share the same name to reduce file size and promote
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hierarchical sharing.
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"""
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def __init__(self):
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# A dictionary of modules indexed by module type
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self.modules = {}
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# These are the indices to append to name to make unique object names
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self.module_indices = {}
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# A dictionary of instance lists indexed by module type
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self.objects = {}
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def reset(self):
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"""
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Clear the factory instances for testing.
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"""
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self.__init__()
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def create(self, module_type, **kwargs):
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"""
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A generic function to create a module with a given module_type. The args
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are passed directly to the module constructor.
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"""
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# if name!="":
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# # This is a special case where the name and type don't match
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# # Can't be overridden in the config file
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# module_name = name
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if hasattr(OPTS, module_type):
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# Retrieve the name from OPTS if it exists,
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# otherwise just use the name
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module_name = getattr(OPTS, module_type)
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else:
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module_name = module_type
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# Either retrieve the already loaded module or load it
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try:
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mod = self.modules[module_type]
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except KeyError:
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c = reload(__import__(module_name))
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mod = getattr(c, module_name)
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self.modules[module_type] = mod
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self.module_indices[module_type] = 0
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self.objects[module_type] = []
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# Either retreive a previous object or create a new one
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for obj in self.objects[module_type]:
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(obj_kwargs, obj_item) = obj
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# Must have the same dictionary exactly (conservative)
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if obj_kwargs == kwargs:
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debug.info(1, "Existing module: type={0} name={1} kwargs={2}".format(module_type, obj_item.name, str(kwargs)))
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return obj_item
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# Use the default name if there are default arguments
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# This is especially for library cells so that the spice and gds files can be found.
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if len(kwargs)>0:
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# Create a unique name and increment the index
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module_name = "{0}_{1}".format(module_name, self.module_indices[module_type])
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self.module_indices[module_type] += 1
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debug.info(1, "New module: type={0} name={1} kwargs={2}".format(module_type,module_name,str(kwargs)))
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obj = mod(name=module_name,**kwargs)
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self.objects[module_type].append((kwargs,obj))
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return obj
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# Make a factory
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factory = sram_factory()
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@ -17,9 +17,8 @@ class pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from pbitcell import pbitcell
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import tech
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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OPTS.num_r_ports=1
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