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Fix error of no control bus width

This commit is contained in:
Matt Guthaus 2018-11-28 15:42:51 -08:00
parent d99dcd33e2
commit 25ae3a5eae
1 changed files with 1 additions and 1 deletions
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2
compiler/sram_1bank.py
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@ -113,7 +113,7 @@ class sram_1bank(sram_base):
# Add the col address flops above the bank to the right of the upper-right of bank array
if self.col_addr_dff:
col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.central_bus_width,
col_addr_pos[port] = vector(self.bank.bank_array_ur.x + self.bank.m2_gap,
self.bank_inst.uy() + data_gap + self.col_addr_dff_insts[port].height)
self.col_addr_dff_insts[port].place(col_addr_pos[port], mirror="MX")