We really want lazy processing of concatenation because it has multiple
inputs and lazy processing should (in theory) prevent redundant and
useless propagations through the net.
But enabling it seems to cause many tests in the regression test suite
to fail to compare their results. There are races in many tests that
are interacting badly with this feature. So for now, ifdef it out.
It doesn't really make any sense to do lazy processing of part selects,
but it is possible to use the part select position to more toroughly
check for changes in output and suppress non-changes. In particular,
we only need to check that the output part actually changes, and by the
way we only need to save those bits for the next go-round.
We do want to make sure that the very first input causes an output,
though, so that time-0 values get propagated.
This is not a solution to all the problems, but is a better catch-all
then what is currently there. Allow the index field to be a T<> that
accesses the thread to get the address index.
Note that the lexor.lex currently returns the T<> as a T_SYMBOL, and the
users of T_SYMBOL objects need to interpret the meaning. This is
probably not the best idea, in light of all the other *<> formats that
now exist.
Part select of parameter names is fixed up to be structurally similar
to part select of signals, and also to behave similarly. (Though not
identically, for reason.)
Part selects to signals are allowed to be off the ends of the signal
itself. The bits that are beyond the vector return X. This may mean
creating constant X bits on one or both ends of the result.
This patch cleans up some of the code to use common compiletf
routines where appropriate. It also adds code to print the
number of extra arguments and cleans up the messages a bit.
The vvp_net_t objects are never deleted, so overload the new operator
to do a more space efficient permanent allocation.
The %assign/v instruction copied the vvp_vector4_t object needlessly
on its way to the scheduler. Eliminate that duplication.
The concat and resolv functors are best evaluated lazily, because each
evaluation is costly and there is a high probability that an evaluation
will be invalidated when new input comes in.
Also optimization the recv_vec4_pv method of the resolver, which is
commonly used, and adjust the order of handling of vvp_fun_part to
work more efficiently.
The vvp_vector8_t constructor and destructor involve memory allocation
so it is best to pass these objects by reference as much as possible.
Also rework the resolver functor to only perform resolution after inputs
are in so that it doesn't get needlessly repeated. This eliminates many
resolve function calls, as well as activations throughout the net.
Also have the islands take more care not to perform resolution if the
inputs aren't really different.
Parameter value ranges support the exclude of a point as well as
range, so add the syntax to support that case. Internally it is
handled as a degenerate range, but the parse and initial elaboration
need to know about it.
If a memory word was accessed before it was defined the
code was returning a zero width vector result. Now it
returns an appropriately sized vector of 'x'.
The memory opcodes %assign/mv, %load/mv and %set/mv
were removed by a previous patch. This one removes
the documentation from opcodes.txt. It also removes
the documentation for the .mem* statements for the
same reason.
Recursive branch resolution was scanning every branch end, even though
many branch ends share ports and need not be repeatedly scanned. Handle
marks and flags to cut off recursion where it is not needed so as to
save much run time.
Conflicts:
tgt-vvp/vvp_scope.c
Note that the draw_net_input.c takes in a lot of the codes that used
to be in vvp_scope.c, so some changes may have been lost.
This patch cleans up the dump routines and adds file and
line number information for errors. It also adds some of
the missing MemoryWord properties so they can now be
dumped and monitored correctly.
This patch adds $simparam and $simparam$str from Verilog-A.
The analog simulator parameters return 0.0 or N/A. The
vvp_cpu_wordsize system function has been moved into the
$simparam call and is now named CPUWordSize.
This patch also starts the factoring of common code in the
vpi directory. Some routines were renamed.
The priv.c file was renamed to sys_priv.c to match the
include file.
System functions can now have strings put to their output.
Rather then join islands while branches are initially created, save the
island creating for the end. This way, the process is actually recursive
and greedy, reliably collecting branches into islands without conflict.
Fold the bi-directional part select into the pass switch (tran) support
so that it can be really bi-directional. This involves adding a new
tranvp device that does part select in tran islands, and reworking the
tran island resolution to handle non-identical nodes. This will be needed
for resistive tran devices anyhow.
The draw_net_input function is modified to account for nexus that is
a port of an island. Draw the ports (and the islands if necessary)
to the island and use the port output for the nexus instead of the
port input. This allows the bi-directional behavior of the port to
interpose itself in the data flow.
In this process of these changes, the draw_net_input function was
reorganized, and all the considerable amount of code for it was
moved to a file of its own. (vvp_scope.c is pretty unruly.)
NetTran devices must be collected into islands because they are all
a bi-directional mass. This is how vvp will process them and the code
generator will need a head start organizing them.
The vvp_island classes are added, as well as support for tranif nodes
that use this concept. The result is a working implementation for
tranif0 and tranif1.
In the process, the symbol table functions were cleaned up and made
into templates for better type safety, and the vvp_net_ptr_t was
generalized so that it can be used by the branches in the island
implementation.
Also fix up the array handling to use the better symbol table support,
and to remember to clear its own table when linking is done.
The code generator was reading the wrong node of a bi-directional
part select. This happens exclusively with part selects passed to
bi-directional ports, so was rare. The result was that the non-part
selected part may get an incorrect value.
The multiply runs does not need to do all the combinations of digit
products, because the higher ones cannot add into the result. Fix the
iteration to limit the scan.
ivl_switch_scope, ivl_switch_attr_cnt and ivl_switch_attr_val
are non-existent routines and should not be in ivl.def. I also
removed them from ivl_target.h. Cygwin expects that if a routine
is listed in ivl.def that it will find a real implementation.
My previous patch always used an empty file if git was not
available. This patch extends this to use the existing
version.h file if it exists (snapshot, etc.)
The handling of immediate add used to do 16bits at a time. When it went
up to 32bits, the need to work in chunks vanished, but the chunk handling
was still there, this time shifting by 32, which causes problems on 32bit
machines. Simplify the %addi handling to avoid this.
Clarify that operands are typically 32bits, and have the code generator
make better use of this.
Also improve the %movi implementation to work well with marger vectors.
Add the %andi instruction to use immediate operands.
Use high radix long division to take advantage of the divide hardware
of the host computer. It looks brute force at first glance, but since
it is using the optimized arithmetic of the host processor, it is much
faster then implementing "fast" algorithms the hard way.
This instruction adds an integer value to the value being loaded. This
optimization uses subarrays instead of the += operator. This is faster
because the value is best loaded into the vector as a subarray anyhow.
The AND and OR operators for vvp_bit4_t are slightly tweaked to be
lighter and inlinable.
The vvp_vector4_t::set_bit is optimized to do less silly mask fiddling.
This involves defining the API for switches and cleaning up the
elaborated form to match the defined ivl_target API. Also add t-dll
code to support the ivl_switch_t functions, and add stub code that
checks the results.
When processing wide vectors of these operations, it pays to process
them as vectors. This improves run-time performance. Have the run time
select vectorized or not based on the vector width.
Improve vvp_vector4_t methods copy_bits and the part selecting constructor
to make better use of vector words. Eliminate bit-by-bit processing by
these methods to take advantage of host processor words.
Improve vthread_bits_to_vector to use these improved methods and Update
the %load/av and %set/v instructions to take advantage of these changes.
The MinGW system() implementation appears to return the straight
return value instead of the waitpid() like result that more
normal systems return. Because of this just return the system()
result without processing for MinGW compilations.
Older version of the MinGW runtime (pre 3.14) just used the
underlying vsnprintf(). Which has some problems. The 3.14 version
has some nice improvements, but it has a sever bug when processing
"%*.*f", -1, -1, <some_real_value>. Because of this we need to use
the underlying version without the enhancements for now.
snprintf prints %p differently than the other printf routines
so use _snprintf to get consistent results.
Only build the PDF files if both man and ps2pdf exist.
MinGW does not know about the z modifier for %d, %u, etc.
Add some missing Makefile check targets.
These instructions can take advantage of the much optimized
vector_to_array function to do their arithmetic work quickly and
punt on X very quickly if needed. This helps some benchmarks.
If the select of a MUXZ is constant 0 or 1, then we can elide the MUX
in place of a simple BUFZ. This should allow the dead code on the
unused side to be removed as well.
Functions like $monitor need to attach callbacks to array words if
those words are to be monitored. Have the array hold all the callbacks
for words in the array, under the assumption that the monitored words
are sparse.
Array words don't have a vpiHandle with a label, so the %vpi_call
needs a special syntac for arguments that reference array words.
This syntax creates an array word reference that persists and can
be used at a VPI object by system tasks.
Memory words may have part selects assigned, but the code messed up
the testing for the validity of the part select base. This fixes do
detect constant bases so that base validity tests are handled at
compile time.
The tran devices include tran, rtran, tranif0/1 and rtranif0/1. These
are all elaborated as options on a NetTran device. It is still not
clear the best way to present tran devices via the ivl_target.h API.
Add include statements (<cstdlib> for abort()) and a cast.
Necessary and sufficient for successful compilation with
gcc-4.3 (Debian 4.3.0-4) 4.3.1 20080501 (prerelease)
The draw_input_from_net function was being used to access words of
a var array, which doesn't work. Have the draw_input_from_net punt
on that case, and by the way the mux inputs don't need to use that
function, instead they should use the general draw_net_input function
to get the input labels.
It is possible for an array to have 1 word in it, so using the array
count to detect an array is incorrect. Use the ivl_signal_dimensions
function, which is there exactly for that purpose.
Before this, the types of parameters were always logic, only the
width and signed-ness could be controlled. A parameter may take
on implicit real values if the expression were real.
With this patch, the type for the parameter can be explicitly set
to logic or real. This also means that the parameter real valued
expressions need to be more crefully treated, possibly with casting
integral expressions to real values, or real expressions to integral
values.
It is possible for the code generator to create .array/port objects
before the .array object that the port refereces, so use the resolv_list
to arrange for binding during cleanup.
Save tons of space per memory word by not creating a vpi handle for
each and every word of a variable array. (Net arrays still get a
vpiHandle for every word.) The consequence of this is that all
accesses to a variable array need to go through the indexing.
This commit handles the most common places where this impacts, but
there are still problems.
vpi_handle_by_name() was assuming it was always given a valid scope
object. In the context of vpi_chk_error() this is not required and
some users use/abuse the interface by calling the function with invalid
objects expecting a 0 return value. This patch adds an explicit check
for the supported types vpiScope and as an extension vpiModule.
Anything else should be flagged as an error once we have vpi_chk_error()
implemented, but for now it just returns 0.
The arguments to $ungetc() were backwards! This patch fixes that
and adds a bit more checking to the compile_tf routine. It still
needs more work, but that can wait for the major system function
clean up I have planned when I can find the time.
It is a quirk of the $signed() system function that the argument
is converted to signed, but the operation that is performed is
not changed. So arithmetic operators on unsigned arguments inside
a $signed() expression still perform unsigned arithmetic.
The pform is now translated/elaborated into NetScope objects. All that
remains is to check the parameter values against the ranges. This is
to be done in the evaluate_parameters() method.
A recent change to sb_to_idx() made it return a signed value
where it previously returned an unsigned value. This patch adds
explicit casts to remove the two signed vs unsigned comparison
warning messages.
Handle parameter value ranges as far as the pform. The +-inf expressions
are not handled yet, nor is the single value exclude, but the other
cases are handled.
The VAMS-2.2 LRM syntax does not include a semicolon after the nature/
discipline name, but the 2.3 LRM does. Effectively, that means that
the simicolon is option from now on.
Fix
elab_expr.cc:1561: warning: comparison between signed and unsigned integer expressions
caused by revised prototype of NetNet::sb_to_idx() in
commit dfb7bf5211
Pform parse enough of the natures that they can be mapped and the
disciplines can bind to them. Since Verilog-AMS expects natures to
be declared before use, we can do the binding early.
The VAMS-2.3 specification says that discipline and nature declarations
have a semi-colon after the identifier, but the disciplines.vams in
the appendix does not. Initial guess what that the disciplines.vams
is correct, but I've been told that the syntax is correct and the
disciplines.vams file is not.
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
This is part of the standard disciplines header file, with enough
syntax to part the natures and disciplines included. Don't do anything
with the parse results yet.
The Verilog LRM specifies that it is legal to give constant part
selects that are beyond the bounds of the identifier being selected.
But elaboration was flagging that as an error. This patch changes it
to a warning, and handles the cases by generating 'bx bits as needed.
The elaborator improperly allowed user function call nodes to take on
the expression width requested of them. The result was that generated
code had junk pad bits in certain cases.
When calculating 0^z with constant arguments, make sure the result is
x. This problem only happens when the arguments are constants and the
expression is calculated at compile time.
Verilog does not allow macro expansion in strings, and that's that.
But sometimes people want strings of a macro expansion, so add a
stringify syntax that does the trick.
Verilog-AMS supports scaled real numbers, where the "e<N>" (scientific
notation) is replaced with engineering scales from "a" (atto-) to
m (milli-) and "K" (kilo-) to "T" (tera-). This syntax can be handled
way down in the lexor.
IEEE1364 has specific names for the various generations of Verilog that
are supported. Icarus Verilog should stick to those names for selection
the language feature set.
In the process, the extensions that were tied to the 2x generations
are pulled out out and given their own enable flags. The makes all the
feature control more regular and understandable.
This patch adds a new system function $vvp_cpu_wordsize. It returns
the size of the underlying CPU word (long) in bits. This function
can be used to write fully portable tests for the test suite. Other
functions will be added as needed.
The abs() function needs to be able to turn -0.0 into 0.0. This proved
to be too clunky (and perhaps impossible) to do with tests and jumps,
so add an %abs/wr opcode to do it using fabs().
The min/max functions need to take special care with the handling
of NaN operands. These matter, so generate the extra code to handle
them.
Fix when sign extending an expression that the result is also signed.
This bug caused some arithmetic operations (with extended arguments)
to not notice that they are signed.
Also be more robust in noticing that comparisons are signed and should
generate the right code.
This patch adds file and line information for parameters and
local parameters. It also adds file/line stubs for signals in
the tgt-* files. It adds the pform code needed to eventually
do genvar checks and passing of genvar file/line information.
It verifies that a genvar does not have the same name as a
parameter/local parameter.
In continuous assign expressions, the abs() operator can't easily be
burried in generic unary handling, so add the IVL_LPM_ABS type and
generate it as needed.
The va_math module implements functions that are optional in base
Verilog but included in Verilog-AMS. So automatically include the
module if -gverilog-ams is given.
The va_math module implements functions that are optional in base
Verilog but included in Verilog-AMS. So automatically include the
module if -gverilog-ams is given.
Implement in behavioral the abs/min/max operators for real values.
The parser treats these builtin functions as operators, unary or
binary, and elaborates them appropriately.
Also add enough code generator support to handle real valued expressions
in thread context.
Verilog-2005 defines the base-10 log function to be $log10. This makes
sense because in C the log() function is the natural log. So add the
$log10 function.
Since there may be legacy code that uses the $log function, leave it
defined, but we should consider at least printing a warning when the
$log function is used.
Verilog-AMS recommends that users use the system-function style
math functions, but supports traditional style math functions for
portability. Add the keywords and parse the traditional Verilog-A
functions, and handle them as calls to the equivilent system
function.
Add the -gverilog-ams flag to the driver, and the begin_keywords support
for VAMS-2.3 keywords. With this, the infrastructure is in place to
start pulling in features from Verilog-AMS.
The begin_keywords directives manage a mask of keyword sets that are
active at a given moment. This patch makes the lexor actually test
the given keyword against the mask. If it matches, return the keyword
id, if it is disabled then it is an IDENTIFIER.
Package builders/managers find the DESTDIR variable convenient for
installing into a temporary target for building a package. This adds
the DESTDIR varilable to the root makefile.
Also, clean up the verilog.spec file to reduce redundancy so that
maintence for releases is easier.
1364-2001 does not allow a replication count of zero, but
1364-2005 allows them when the replication is enclosed in
a concatenation with other valid bits. This patch adds
code to perform these checks for procedural expressions.
Because of the NetNet object must have a width greater
than zero a replication used in a continuous assignment
can never have a count of zero.
This patch makes sure that objects either support vpiFile
and vpiLineNo or adds dummy code so that a runtime error
will not occur when accessing these properties. It also
returns 1 for the size of real variables and adds a
simplified vpiIndex that matches the Memory interface.
The begin_keywords directive allows the source code to select keyword
subsets so that a bit of code that uses identifiers that class with a
newer version of the standard can still be compiled.
This patch adds code to push the file and line information
for scope objects (modules, functions, tasks, etc.) to the
runtime. For modules, this includes the definition fields.
The va_math.vpi module implements systen-function versions of the
Verilog-A math functions. This library was contributed by Cary R.
Also add the constants.vams include file. This is pretty much
direct from the Verilog-AMS LRM.
This patch adds ifnone functionality. It does not produce an
error when both an ifnone and an unconditional simple module
path are given. For this case the ifnone delays are ignored.
This patch does a better job of recovering from an error in a
task or function definition. This prevents the compiler from
printing many irrelevant error messages.
This patch adds the functionality to tasks/functions to handle the
declaration of multiple ports using a single ANSI declaration. It
also deletes the old range vector before it adds the new one. The
tasks and functions are different than modules so we need to copy
the range for them.
Several places in Icarus Verilog try to get the bits of the integer
part of a double by casting to unsigned or unsigned long. But that
causes some compilers to generate smart code that converts all values
less then 0 to 0, even though we are after the bits, not the math
value. So be careful to do this cast only to non-negative values and
uminus the bits if necessary to get exactly what we want.
Signed-off-by: Stephen Williams <[email protected]>
Fix handling of cases where multiple specified delays are activated
for a given output. Need to apply the standard selection criteria
that gets the minimum value.
The %sub instruction didn't have the efficent implementation that
the %add instructions used. Update subtraction to use the array
method, so that it gets the same performance benefits.
The vvp_vector4_t often receives the results of vector arithmetic.
Add an optimized method for setting that data into the vector. Take
into account that arithmetic results have no X/Z bits, etc.
Logical and/or take as inputs condition expressions, which are scalar
expressions. Be sure to reduce vectors using proper logic to get the
right condition value.
This patch adds check to determine if an always block has delay
in it or not. If there is no delay a runtime infinite loop will
occur. For the indeterminate case it will print a warning message
if the new -Winfloop flag is given. This flag is not part of the
-Wall check!
When generating a real expression you can have bits of the
expression that use vector only operands. When this happens
evaluate that part of the expression as a vector and then
convert it to a real value.
On some systems, 1UL<<X will make a mess if X is the size of
an unsigned long. This especially seems to be a problem on i386
systems. Protect those shifts in the vvp_net.cc.
When left-shifting unsized constants in self-determined contexts, the
constant value is normally pared down to its minimum required width.
But this practically guarantees loss of bits. Instead, detect this
special case and give the unsized constant a width of an integer.
Still allow for the super-special case that the shifted value and the
shift amount are constants. In that case, the result width (and value)
can be calculated precisely and there is no need to resort to default
widths.
This patch uses the true delay expression count not the truncated
one to check that the number of delay expressions is correct.
It also prints the actual number of expressions it found when
printing the error message.
By slightly altering the vvp_bit4_t encoding, a few simple
optimizations become possible. By making Z==2 and X==3, the
conversion from X/Z to X is a simple shift-or, and this can
be used to reduce the size of some of the bit4 operators.
In previous incarnations of the vvp runtime, bit vectors were passed
around as arrays of unsigned char that charried bit4 vectors. That
is no longer used. Remove the last vestiges of that dead code.
Remove dependencies on vvp_bit4_encoding outside of the vvp_net
core types. The table_functor_s class was the worst offfender and
was barely used, so it is now removed completely. There are a few
opcodes in vhtread.cc that also make vvvp_bit4_t encoding
assumptions (and used casts) and those have been fixed. There
were also various VPI interface functions that are fixed.
The vvp_vector4_t holds 4-value logic. This patch changes the encoding
of 4-value bits in the vector to use separate A- and B bit vectors,
with the B- vector signaling the A- bits that are not 0/1. This
allows rapid conversion to 2-value logic, and rapid tests for X
and Z values.
Update the rules for parsing user function definitions to allow
Verilog-2001 ANSI style port declarations. In the process, also
unify with the user task port declaration so that the types don't
diverge. The rules are the same for both, with the extra constraint
that function ports must all be input. This latter rule is checked
later, during elaboration, so that the task/function pform code
can be shared, and better error messages can be generated.
This patch fixes deassign to allow it to unlink from a driver.
It also zeros the cassign_link and force_link pointers after
they have been unlinked. Not doing this will cause an assert
if deassign/release are called multiple times (variable only).
commonly, the make install is run in a compiled directory by a
different user (i.e. an administrator) that doesn't necessarily
have write access to the build directory. This patch fixes it so
that the test that the version.h is up to date doesn't need to
write a temporary file in the build directory.
It also makes sure that if there is a real need to update the
verion.h, and it is not writable, then properly fail the build.
Passing preprocessor definitions forward into library cells was broken
by this bug in processing the precompiled macro values that were written
by the main preprocessor.
Detect thread bit allocation failures and fail gracefully. Print an
error message that points at the expression in question, and return
with an error code so that the compiler exits with an error.
When constant values are added to get another constant value, and the
expression is not otherwise a fixed size, then trim the result to
prevent unbounded expansion of unsized expression with.
In the process, find and fix a bug in the vtrim function that caused
an assert if trimming were not possible for an unsigned value.
This patch fixes the elaboration of parameters in a continuous
assignment to only pad the constants to their defined width.
Previously they were padded to the l-value width which resulted
in a vvp runtime error. This appears to be because the width
for padding is the defined width, but the constant is printed
using its internal width which previously could be larger than
its defined width.
These constants are local nets so I added that flag as well.
This patch adds the ability to assign/deassign a bit or part select.
It also cleans up the code and fixes some problem in the forcing of
strength aware nets.
When printing the strength information for a multi bit net this patch
adds an underscore between the individual bit strength values. This
makes it easier to see the individual bit values.
A patch to insert the version string from git broke compilation when
the source was not a git repository or when building in a read-only
source tree. This patch avoids breaking compilation by using a
graceful failure mechanism for generating the version string and does
not write to the source tree.
Rework the MUXZ and MUXR code to use an enum instead of plain
integers for the select input state. This makes it more obvious
what is actually going on.
This patch adds a flag to the MUXZ object to make sure that it will
run at time zero if needed. If this is not done the default Z result
may not be overridden by an X result.
This patch adds a %assign/av/d opcode. This is a version of %assign/av
that allows a delay expression. Ultimately this allows a dynamically
indexed array to have a delay expression (non-constant delay value).
This patch removes the overly optimistic lookaside save for a signal
that has been set (%set/v). This is incorrect because if a force or
assign are active the value will not be set as expected.
Parameters with vector descriptions that are not zero based and
are used in net contexts should generate the properly ranged
temporary signals. This causes subsequent part selects to work
out properly.
During elaborate_sig, the code to detect implicit wires did not
properly account for the possibility that the name is that of an
explicitly declared parameter.
This patch add (I believe back in) the < and > characters to the
general T_SYMBOL regular expression. The match was also moved after
the special T_SYMBOL cases so that flex would match them correctly.
Flex matching rules are longest or if a tie the first.
This patch adds code to prevent the broken synthesis code in
the development branch from core dumping. Broken code here
refers to the Icarus code not a Verilog file.
This patch fixes a delete[] vs free problem in the NexusSet
class. The items_ array was being allocated with malloc/realloc
and freed with delete[]. The quick fix was to replace delete[]
with a call to free(). A better fix would probably be to rework
the class to use a vector.
The default nettype was not always being set. This patch
modifies the NetScope constructor to get the default
nettype from a parent if it exists. It is set to NONE if
a parent does not exist.
This patch fixes some allocation problems (mostly in the parser
and lexor relating to identifiers). It also fixes a couple places
where uninitialized variables were used. All found with valgrind.
There are still 100 tests that have problems. Many of these appear
to be related.
Macro argument substitution used to just use strstr() to
find an argument that needed to be substituted. This is too
aggressive. It would do argument substitution in the middle
of keywords and other identifiers. A new routine is used
that verifies the character preceding the match is not
a normal identifier character [a-zA-Z0-9_$].
Binary bit based operators were not padding arguments if they had
different widths. The reduction operators and ! were not correctly
evaluating their arguments in a self-determined context.
vvp did not have the ability to handle real parameters.
This patch fixes that omission. Parameters are only used
by vpi calls to get compile time information.
Problems with signed expressions that are set to parameters and
that include multipliciation exposed a few bugs in the calculation
of signed multiply. Fix this and add some improved diagnostics.
It is questionable, but probably legal, for expressions passed as
arguments to input ports of various kinds of gates to implicitly
declare nets. This patch allows the scan through different types
of expressions for implicit nets.
The elaborate_sig handling here does not test for the legality of
having a non-trivial expression as argument to a port. For example,
it is definitely NOT legal to have r-value expressions passed to
output or inout ports. But that will be checked for later when the
instance is elaborated for real.
Threads used to be deleted when they finished processing code.
The problem with this is that some of the code could be
rescheduled to run at rosync ($strobe, etc.). This allowed the
thread data the code depended on to be reaped too soon. This
patch uses a new queue to schedule thread deletion. The queue
is processed after rosync has finished.
This patch makes the muxz and muxr functors schedule events
instead of directly calling vvp_send_*(). This prevents the
code from going into an infinite loop when the output feeds
back to the select.
This patch only applies to the ternary operator when used in a
continuous assignment. It adds short circuiting when the expression
is a constant true or false. It does not optimize the special case of
a constant 'bx expression with constant T/F expressions.
This patch enhances dump() for function definitions, by indicating a
signed result with a prepended "+" and also printing the MSB and LSB.
This matches other dump() routines. It also prints the arguments with
the same information. The arguments also include their type "input",
"output" or "inout".
If implicit nets are declared during elaboration, then the success
of binding during elaboration will depend on the order of the code
in the source file.
The dup_expr() function for NetESignal was not copying the word_
expression. This would cause an individual array access to turn
into an entire array access. The file and line information was
also not being set correctly.
An assert() in tgt-vvp/eval_expr.c was also replaced with an
exit() since the appropriate information was already being
printed.
This patch adds functionality to do a bit or part select release
when a constant value is forced to the net/register. It also adds an
error message when the user tries to force a signal to a bit/part
select. This is not currently handled by the run time, so is now
caught in the compiler (tgt-vvp). Where when this functionality is
needed, it will be easy to know what to do instead of trying to track
down some odd runtime functionality.
What this all means is that you can force a signal to an entire
signal or you can force a constant to any part of a signal (bit,
part or entire) and release any of the above. Technically the
release of a constant value does not have to match the force.
The runtime verifies that if you are releasing a signal driver
it is being done as a full release. I don't see an easy way to
check this in the compiler.
To fix the signal deficiencies we need to rework the force_link
code to allow multiple drivers and partial unlinking. Much of
this is in the runtime, but the %force/link operator may also
need to be changed like I did to the %release opcode.
The IVL_EX_NONE type was not displaying any message and default did not
use the new ivl_expr_{file,lineno} functions to get the source location.
This patch remedies these problems.
vpi_put_value can mimic force and release with vpiForceFlag and
vpiReleaseFlag flags to the vpi_put_value call. With this patch,
the infrastructure is added to allow the flags argument to be passed
to the dispatched put_value function, and for signals handle those
flags as force/release of a net.
This patch reworks much of the ternary code to short circuit when
possible and supports real values better. It adds a blend operator
for real values that returns 0.0 when the values differ and the value
when they match. This deviates slightly from the standard which
specifies that the value for reals is always 0.0 when the conditional
is 'bx. There are also a couple bug fixes.
These fixes have not been ported to continuous assignments yet.
Ternary operators used at compile time and in procedural assignments
should be complete (short circuit and support real values).
When a bit port of a module instance is connected to a vector
argument, the MSB module instance should be connected to the MSB
of the vector argument. This matters only in the rare case that
the %m is used. It also makes wave dumps come out right.
The updates to the do_include code destroyed the
handling of absolute paths; all of the code that
handles buffer-switching was erroneously placed
in just the relative-path branch. Thanks go to
Cary R. for pointing out the problem.
Now the common code has been extracted yet again,
and the notorious goto statement has been used
in favor redundancy.
The test vvp_reg.pl produces the same output as
before, so hopefully nothing new is broken.
Signed-off-by: Michael Witten <[email protected]>
Normally processes are found in the lexical scope of a module, but
there are special cases where processes (other then task/function
definitions) are in other lexical scopes. The most likely case is
initilizations that are in the lexical scope where the assigned
variable is declared.
In the process, the behaviors list is kept in the base PScope class
instead of the Module or any other derived lexical scope class.
Case-generate alternatives create sub-scopes that need to be scanned
by the scope scanner in order to get function definitions etc. that
are defined lexically within generated scopes.
This patch converts a constant real index to an integer value when
defining an array. This can happen when using 2**8 which returns a
real value since the operands are signed.
draw_number_bool64() in tgt-vvp/eval_bool.c was using %ix/load to
load immediate values into registers greater than three. The problem
was that of_IX_LOAD() in vvp/vthread.cc was masking off the upper
bits. This was putting the results in the wrong register. This patch
removes the bit masking from of_IX_LOAD() and updates the %ix/load
documentation.
The file lexor.lex was beginning to suffer a catastrophic
increase in entropy due mainly to the mingling of spaces
and tabs--an age-old problem that often finds itself as
the subject of many a religious war.
The key rule: Make it consistent in as many editors as
possible; this was achieved by converting all hard tabs
into soft tabs (composed of spaces) of width 4.
I couldn't help but make modifications to the code as I
tabifified, but most of the changes are strictly style.
While maintainers generally treat large scale whitespace and
formatting changes with much caution, I believe that the code
is now much more maintainable; moreover, the test suite
produces the same results as before.
Signed-off-by: Michael Witten <[email protected]>
Macro names cannot be compiler directive names.
Such trespasses are now recognized and reported:
(1) Offending `define lines are skipped.
(2) Offending macros meant to be expanded
are replaced with nothing.
Signed-off-by: Michael Witten <[email protected]>
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
The ordering of the logic was a little strange before.
Also, there were unnecessary operations, like the assert
and the include_dir[0]=0 business.
Signed-off-by: Michael Witten <[email protected]>
Discussions online and "standards" documents are never
conclusive, but the code that was present suggests that
iverilog adopts the sane practice of resolving relative
paths against the directory of the file that is currently
being processed.
Unfortunately, when a relative path is made absolute, the
code forgot to update the necessary include_stack_t object.
This has now been fixed.
Signed-off-by: Michael Witten <[email protected]>
When the lexical analyzer encounters and EOF, the
analyzer invokes yywrap() to determine what to do
next. The function determines one of two paths of
execution:
(1) If yywrap() returns 0, then the analyzer
assumes that yywrap() has setup a new input
source, and so scanning continues.
(2) If yywrap() returns non-zero, then the analyzer
assumes that yywrap() has not setup a new input
source, and so the analyzer proceeds to run the
matching EOF action (the default of which invokes
yyterminate()).
NOTE: The analyzer does not touch the start condition.
The old implementation was using yywrap() to destroy the current
input source and setup the next one. However, this causes problems
when the analyzer is in the middle of parsing some directive:
(1) Because yywrap() is called before any EOF action,
the include_stack_t structure is destroyed before
being used in the EOF action; the result is a segfault.
(2) Because yywrap() does not change the start condition,
any EOF action would occur completely out of context;
however, because of (1), this problem never cropped
up.
The new implementation simply:
(1) Employs "%option noyywrap", which effectively causes
the analyzer to act as though yywrap() produces a non-zero.
(2) Renames yywrap "load_next_input".
(3) Calls load_next_input() explicitly in exhaustive EOF actions,
so that control is more fine grained.
The added benefit is that the code that finishes parsing EOF terminated
directives now works properly; `include and `define directives previously
segfaulted in such situations.
Signed-off-by: Michael Witten <[email protected]>
This variable was used in yywrap purportedly to obviate
hidden access to a file that should be closable.
After investigating the code flex produces, it would
seem that these fears are unfounded.
Signed-off-by: Michael Witten <[email protected]>
The verilog preprocessing language is sufficiently simple
that the parser may be implemented by hand on top of the
lexical analyzer.
In fact, ivlpp was already implemented in this way; relevant
[bison] parser files specified no grammar, and the parser
entry-point (yyparse) was simply an indirect use of the lexical
analyzer (yylex).
Therefore, parse.y has been removed, invocations of yyparse()
have been replaced by yylex(), references to bison generated
files have been removed, and Makefile.in has been updated
accordingly.
Signed-off-by: Michael Witten <[email protected]>
This patch fixes two problems. The first is that thr_check_addr()
was being used inconsistently. It should be passed a real address,
but the resize of the vector should be at least one more than this
address. The extra and unneeded CPU_WORD_BITS was also removed
from the routine.
The second problem involved an invalid memory access in
vvp_vector4_t::set_vec() when the vector being copied was an integer
multiple of the machine word width. Under this condition there would
be no remaining bits that needed to be copied but the routine was always
trying to copying some remaining bits. This code is now only executed
when there is a remainder.
Neither of these appear to be causing runtime problems. The second one
was found with valgrind. The first were found while tracking down the
second problem.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
This patch adds support for delaying constants at time zero. It also
cleans up the code in elab_net.cc to use this capability instead of
building it with an extra BUFZ to carry the delay information.
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
This patch adds a real error message instead of an assert when
someone attempts to release a part or bit select. I plan to work
on the real functionality soon.
This patch adds the power operator for signed bit based values
in a continuous assignment. It also fixes a few other power
expression width problems. The expression width is still not
calculated correctly, since the correct method can produce huge
possible bit widths. The result is currently limited to the width
of the native long. This is because lround() is used to convert
from a double to an integer. A check in the code generator protects
the runtime from this limitation.
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
This patch adds the power operator for unsigned bit based values
in a continuous assignment. It also refactors the power code for
normal expressions and continuous assignments.
User functions called in a continuous assignment were not getting
their scope mangled. This is needed to handle arrayed instances and
possibly other things.
This patch fixes some bugs in the implementation of signed integer
division with wide operands in constant expressions and adds support
for signed integer modulus with wide operands in constant expressions.
It also removes a few redundant lines of code.
Incorrect trimming of unsigned verinum values was causing the
compilers unsigned constant verinum pow function to give
incorrect results. This patch restores the pow compile time
optimization and fixes the trimming to always leave a single
zero in the MSB.
This patch adds bit based power support to normal expressions.
It also pushes the constant unsigned bit based calculation to
the runtime until the bit based method can be copied to the
compiler. Continuous assignments also need to use this type
of calculation.
Currently, if a localparam declaration does not include a type or
range, the RHS expression is cast to an unsigned value. This patch
changes this to make the localparam inherit the type of the RHS
expression, as is done for parameter declarations and is specified
by the Verilog-2001 standard.
This patch adds a check and prints a warning message when the power
operator is used with unsigned bit based values. It also fixes a couple
of typos and adds an asserts if the above power operator happens to
get to the tgt-vvp back end.
Fallout from me trying to understand the origin of pr1780480
and pr1830834. Too bad I don't understand c++ and vvp as
well as I understand English!
(Spelling and grammer fixes in comments. -ed.)
vvp/main.cc was including asm/page.h on GNU/Linux
systems, though that file does not often exist and
is not necessary.
Signed-off-by: Michael Witten <[email protected]>
Padding and continuous assignment caused problems if the continuous
assignment includes a delay. The problem is that the padding was
not necessarily included in the delay. Rework the elaboration to
make sure the padding is indeed included in the delay.
This patch adds some checks to verify that shifts, the reduction
operators and the bit wise operators are not used with real values.
It also includes a few other cleanups.
This patch makes sure the delay is calculated correctly when only some
of the bits change and you are comparing against the initial (t0) value.
Basically you have to check the initial value against all the bits in
the new signal not just the first bit since the order that bits change
is not deterministic.
This patch add delays in continuous assignments for the shift operators,
concatenations and replications. It also reports an error if the user
attempts to take the modulus of a real value.
This patch uncovers a couple other problems in the system. I am trying
to fix one of them. I will report the other problem shortly.
This patch fixes some of the delays in bit based continuous
assignments (unary -, unary +constants, string constants,
reduction operators and user functions).
Use draw_lpm_output_delay() in all functions that need it.
Addresses pr1879226 on a couple of levels. Analysis:
NetNet* PEBinary::elaborate_net_shift_() didn't flag dist==lwidth
as a case where all bits of the input are shifted away, which made
it create a real concatenator for this case. It attempted to create
NetNet*tmp with zero width, which doesn't work; (lsb,msb) ends up
as (0,-1), which is later interpreted as a 2-bit wide net.
Added an assert to the NetNet constructor to catch any other lurking
attempts to create zero-width nets.
Added short-circuit code to handle the case where all bits of the input
are shifted away. This case used to be "handled" by an assert failure.
When used in continuous assignments, user defined functions may have
delayed output. Handle that by generating the proper .delay node when
needed to delay the output of a .ufunc node.
Allow user defined functions to take real value arguments and return
real value results in net contexts. Use the data type of the nets
attached to the ports to define the data types of the arguments and
return value.
There was much redundant code in the compile-tile handling of the
less-then and greater-then of constant expressions, and much of it
was buggy. Unify much of the code and squeeze out the bugs so that
compile-time evaluations come out correctly.
The compiler attempts to precalculate the results of <= comparisons.
Fix a few corner cases where the arguments are signed. Also fix the
important test of constant against non-constant where we try to test
if the non-constant value can possibly make the test fail.
When conditional delays are in use, it is sometimes possible for there
to be no delays available for a given input event. In that case, skip
the delay processing for that case instead of crashing.
Previously only the logical operators (~, &, |, ^, etc.) supported a
delayed value in a continuous assignment. This patch should extend this
to all operators. An extensive check of real values was done. The same
will be done shortly for bit based nets.
Checks for constructs currently unsupported in continuous assignments
provide a more explicit message (** operator, real user functions,
{!, && and ||} operators with a real argument).
Rework the encoding of a real value in the Cr<> label to be similar to
the format used by the %loadi/wr instruction. This mantissa-expoment
format better carries all the bits of the desired real value with
plenty of fidelity and range.
The continuous assignment multiply expands vectors to the sum
of the two widths. This is correct for bit based vectors, but
for real variables it should always be one bit wide.
The sys_funcs table should be left to those functions that are handled
internally by the compiler. Really, the internal sys_funcs table is a
legacy from the days before the compiler supported system function
tables in the .sft format.
System functions used in a continuous assignment must be defined
in the system function table since the name of the system functions
is kept in this definition. The default name is NULL which causes
problems. This patch add $rtoi to the system table and adds a check
for a NULL name.
The comment that shows the intended value for real constants was
being printed with a %f. This is wrong for large or small values.
This patch changes the %f to a %g to get more consistent results.
A right shift may generate extra bits to preserve the proper shift
characteristic. This patch replaces the assert that was forcing the
input vector to not be greater than the input port width with code
to only select the required lower bits from the vector if it is
larger than the input port.
This patch adds support for the following statement:
<vector>[<i>] <= #<delay> <value>.
It is a copy with slight modification of code from the next
else/if clause.
The nodangle functor tries to delete NetNet objects that are not used.
But NetNet objects that are addressed by a NetArrayDq should never be
dangling. So make sure the NetArrayDq marks the target NetNet correctly.
This patch adds a new opcode %load/avp0 that is used to load a
word from an array and add a value to it. %load/vp0 was
changed/fixed to do the summation at the result width not the
vector width. This allows small vectors to index large arrays with
an offset. A few errors in the opcodes.txt file were also fixed.
In nets, if system functions return a real value the function lookup
was getting the correct width, but was also setting the width to 0,
which confused down-stream net handling. Real-value system fuctions
have a width of 1. (1 real-valued scalar.)
This patch modifies the conversion functions $rtoi, $itor,
$realtobits and $bitstoreal calltf routines to be more efficient.
This is done by caching the vpiHandle to the argument in the userdata
pointer. This eliminated the need to get the argument iterator, scan
and free the iterator.
It also updates the error messages to use the new file and line
number information that is available for system functions. It also
adds a check that verifies the functions are only called with one
argument and makes the errors fatal.
This patch schedules the input value change to .sfuns calls to avoid
potential recursion problems. It also cleans up two put_value calls
that did unneeded loops when putting VectorVals and the width was
greaten than 32 bits.
This patch adds a new flag to vvp "-n" that can be used to make
$stop and hence <Control-C> act like $finish. This may be desired
when using vvp in a non-interactive environment.
tgt-vvp/eval_expr.c uninitialized variables
vpi/sys_display.c uninitialized variables
vvp/vpi_priv.cc deprecated string constant usage
vvp/vpi_vthr_vector.cc deprecated string constant usage
the last entry invokes vpip_name_string() and uses const char *
in the same way as the other 9 callers in vvp/*.cc, the only
difference is that the argument is static instead of computed.
cvs -z3 -d:pserver:[email protected]:/cvsroot/gtkwave co -P gtkwave3
delete CVS logs embedded in files
had to add #define wave_alloca alloca to lxt2_write.h
differences remain relative to upstream .h files:
whitespace
value chosen for LXT*_WR_SYMPRIME
Regarding the latter, Tony writes "Don't worry about the .h file.
The only difference is a considerably larger initial hash size.
If this isn't a problem with Icarus now, it certainly doesn't
need to be bumped up."
Fix data type handling of module ports. When ports are declared
as ports and given data types in different statements, the parser
incorrectly (and silently) dropped the intended data type for the
default LOGIC type.
Rework the ivl_file_table_* interface to be more generic and easier
to use. Also all the vvp examples except for memory.vvp have been
fixed to run correctly with the current vvp. Someone with a bit more
experience will need to fix memory.vvp.
Add the vpiFile and vpiLineNo properties to system functions.
Most other objects have stubs that return "N/A"/0. Interactive
functions (called from the debugger) use <interactive> for the
file name.
Use the precompiled defines file support of the ivlpp preprocessor
to pass defines made in the main program to processed library modules.
In other words, a `define in the Verilog source will be visible to
library modules.
Core preprocessor support for writing out and reading precompiled
defines. The preprocessor can read initial precompiled defines from
any number of specified source files, and can write all the defines
into a specified output file.
With this change, local symbols are not emitted in the vvp target,
but are marked as local. When thus marked, the vvp run time does not
offfer any VPI access and the signals (net or var) are effectively
invisible.
Zero-based part selects are a special case that is handled with
optimized code. Properly handle the part select width to get the
desired padding.
Signed-off-by: Stephen Williams <[email protected]>
The code to handle real functions using the PLI 1 interface was
missing some functionality. This patch fixes that and fixes a
bug in the veriuser.h include file.
The recent changes to vpi_get_str had a minor problem that was
causing a core dump when trying to get the vpiFullName of an
arrayed signal. Basically vpi_get_str is not reentrant so the
name must be duplicated. It must also be duplicated to work with
the free in the code (do not free a result_buf).
Add support for a default, standard, implicit include directory
in the base directory for the ivl installation, where standardized
Verilog header files may be placed.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
Gets rid of a few warning: deprecated conversion from string
constant to 'char*', follows IEEE 1364-2001C 27.10 in more cases,
and fixes at least one real bug (look at the previous use of
strdup/strcat in real_var_get_str() and signal_get_str()).
When evaluating bitwise binary expressions at compile time, get the
signed/unsigned padding correct. Pay special attention to the case
of $signed/$unsigned changing the signedness of the operand.
Prevent an overflow of command line flags if the -Wall argument
is used multiple times, and fix processing of individual flags
that may be in the beginning of the warnings flag buffer.
When user defined function calls are withing a $signed, the result
needs to be properly padded. To make this work, handle padding of
a function result exactly type the padding of a signal vector. this
is natural in that the function return value *is* in a signal vector.
This fixes pr1841300.
This patch fixes the calculation of the scope type in draw_scope.
This code is really only used in the VCD dumper so I commented it
out in the other two. The problem was that the lower scope was
used to calculate the scope type. It is also now an error to try
to draw an invalid scope type.
This patch fixes a number of problems associated with the various dumpers.
1. It catches the problem uncovered in pr1809904 and prevents the core
dumps from happening. It prints a warning message if you try to change
the file after the program has started dumping data to the file.
2. It makes all the dumpers work in the same manner. Before the VCD
$dumpfile was processed at compile time, but the LXT/LXT2 versions
did this at run time. The correct place for this is the run time so
that you can pass the task a calculated name.
3. All the dumpers use common compiletf routines located in vcd_priv.c
4. Make the LXT/LXT2 $dumpfile commands only get the file name and
let $dumpvars actually open the file. This matches the VCD code.
5. Fix the $dumpfile code to allow calculated file names.
6. Make dumpvars without a scope/variable match all toplevel modules
not just the toplevel module the $dumpvars was located in. This
now matches the standard (2001).
7. Simplify the no dumper code (vcdoff.c) and add missing functions.
8. Cleanup the code and messages.
9. vvp can take -none for no dumper.
This patch fixes another minor problem introduced by the process
end of simulation events. Specifically if the compilation has
indicated we should not run do not even start the main event loop.
Parse SDF file annotations of edge sensitive delay paths.
Add vpi support for getting the specified edge sensitivity of
an edge sensitive path, and annotate paths with proper attention
to the edge that is specified for the path.
When loading a part select from the least significant bits, it is
OK to use the %load/v instruction to strip the high bits off. This
allows the zero-based part select to work in one step, without
loading excess bits.
Some patch caused a variable that held the constant base of a part
select to become unassigned. This led to unexplained failures to part
select a signal. Fix by properly detecting the case of a constant base
of 0 for the part select.
The %ix/getv instruction loads an integer register directly from
a signal vector. This is an optimization that an index register
is loaded from an expression is only a signal. It avoids the thread
vector space.
Using the parser supplied error token to get file and line number
information appears to give incorrect results at best and core dump
at worst. This patch uses the closest real token that makes sense
to alleviate this problem.
Use the new array VPI functionality (vpiIndex, vpiParent, vpiArray)
to dynamically generate array word names. The old patch to implement
was mostly reverted.
Add the array related VPI calls. These will be used to generate
the array word name only as needed to conserve space. This patch
also makes scanmem3 from the vpi test work correctly after a
slight gold file update.
Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
The patch for adding support for macros with arguments contained
a leftover debugging aid. This patch corrects the code. It also
should eliminate some compilation warnings.
The functor counters were left over from the v0.8 release. Rework
the counters to be relevent to the current state of vvp.
Signed-off-by: Stephen Williams <[email protected]>
This patch modifies the preprocessor to handle text macros with
arguments. It also fixes a bug that prevented a `line directive
being issued after a multi-line text macro had been instantiated.
The second argument of $sdf_annotate is the scope that is to be
annotated. The argument is optional, and the default is to annotate
the current scope, where the $sdf_annotate is invoked.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds a -D option to iverilog-vpi and updates the manual
page to document this option and some others that were missing.
From c7347239335558b26c873ea5e64d278d1feff38a Mon Sep 17 00:00:00 2001
From: Cary R <[email protected]>
Date: Thu, 29 Nov 2007 10:31:25 -0800
Subject: [PATCH] LD should be based on $CC and not hardcoded to gcc
Fix the default loader so it will be whatever the default C
compiler is ($CC).
---
iverilog-vpi.sh | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/iverilog-vpi.sh b/iverilog-vpi.sh
index fbccedb..d2512cc 100644
--- a/iverilog-vpi.sh
+++ b/iverilog-vpi.sh
@@ -25,7 +25,7 @@ CXX=@IVCXX@
CFLAGS="@PIC@ @IVCFLAGS@ -I@INCLUDEDIR@"
# These are used for linking...
-LD=gcc
+LD=$CC
LDFLAGS32="@SHARED@ -L@LIBDIR@"
LDFLAGS64="@SHARED@ -L@LIBDIR64@"
LDFLAGS="$LDFLAGS64"
--
1.5.3.4
Handle the special case that the SDF CELL instance is empty. In this
case, the SDF file is requesting the current scope instead of an
instance within the scope.
Signed-off-by: Stephen Williams <[email protected]>
the lexor didn't allow numbers in the IDENTIFIER name,
and the parser wasn't very nice with IDENTIFIER errors.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds the ability to dump array words. The words are only
dumped if they appear in a $dumpvars() statement (they are not dumped
by default). The name used for the word is <array_name>[<index>], so
you can get unexpected name conflicts.
There is also a slight increase in the memory requirements since each
array word now keeps its own name information. In the future we would
like to change this, but that is a much larger rewrite of the array
code in vvp.
This patch also needs the "Prefix escaped identifier ..." patch to
work correctly (the array word name is an escaped identifier).
Comparison operands are signed only of both operands are signed.
If one is unsigned, then they both are unsigned. This does not
affect the signedness of the comparison itself, which is unsigned.
Signed-off-by: Stephen Williams <[email protected]>
Implement extended vvp command line options to control the amount
of detail that the sdf annotator emits while parsing the source
file.
Signed-off-by: Stephen Williams <[email protected]>
Pass parsed SDF delays into the vvp run time as vpiScaledRealTime
variables, and handling the mapping of 2-values to 12-delays.
Signed-off-by: Stephen Williams <[email protected]>
The LXT and LXT2 formats ignore/work with duplicate variables in
$dumpvars() commands, but VCD output includes extra definitions that
may cause some confusion. This patch checks for duplicates and prints
a warning when they are being suppressed.
It also corrects some error messages in the LXT and LXT2 files to not
reference VCD and some other message cleanup.
The min/typ/max default warning was not being produced in all
locations a min/typ/max expression could be used. This patch
adds the default warning code to all locations. It also
modifies the manual page to explicitly state that only the
first ten warnings are printed.
GTKWave needs to have escaped identifiers properly escaped (preceded
with a back slash) in its VCD input. Without this the name may not
display correctly. Even though it is not required, to keep things
consistent LXT and LXT2 formats also prefix escaped identifiers with
a back slash.
This patch causes unnamed generate blocks to be automatically named
using the naming scheme defined in the Verilog-2005 standard. This
is a fix for the problem discussed in pr1821610.
This patch cleans up some of the crashes in the synthesis
code by incrementing the error count as appropriate. This
also removes the three false positives in the test suite
(Sorry-Ran-PASSED). A few other messages will change in
the test suite as well (blocksynth? and basiclatch).
This was causing a core dump for a number of the vpi test cases.
The problem was that they did not need the simulation time, so it
was being set to NULL. The problem was the EndOfSimulation callback
was always setting cb_data.time to the current time. A big problem
when the pointer was NULL. The solution is to only set the time
when the pointer is not NULL
During elaboration certain constants were getting extended with
the MSB. This patch makes that happen only if the constant does
not have a length. At this point most should have a length so
effectively every unsigned value is extended with 0.
For text macro substitutions the lexor did not allow leading underscores.
This patch fixes that omission. All other places that text macros may be
used appear to be correct.
Most types in Icarus support a single array dimension (reals do
not support arrays at all). If you try to use an invalid number
of dimensions the parser will now display an error message.
String values are known to be 2-value bits, so they are natural
candidates for using the movi instruction to load the value in
far fewer instructions. With this patch, up to 16bits (two bytes)
at a time can be loaded per instruction.
Signed-off-by: Stephen Williams <[email protected]>
tgt-vvp was taking strings and processing them as is, but the strings
could contain octal constants. These constants needed to be converted
to binary form before they could be turned into a bit pattern.
CMOS gates like NMOS and PMOS have a strength aware output.
They were missed when the NMOS and PMOS were fixed. "cmos.v"
will now pass in the test suite.
A previous patch I submitted to try and keep the $finish time
events missed the case of an infinite loop that did not advance
the micro time step which then prevents the debugger from
generating a finish (you can interrupt an infinite loop, but you
could not finish out of it). This patch adds a check for a
finish after each debugger call to fix this problem.
When nets are forced by non-constant expressions, the value is linked
to the destination net through a force_link. This patch adds the code
needed to unlink a force/link so that release and new force/links can
work. This fixes pr1735836.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds marks at simulation end if needed and enabled (on
and not over the limit) for vcd/lxt/lxt2 files. End of simulation
callbacks also now have the correct simulation time. The default
file names for lxt and lxt2 now match the vcd file except for the
extension. lx2 is also an alias for lxt2 and the default lxt2 file
extension is lx2. This matches what GTKWave expects. Any lxt2
diagnostic output print LXT2 instead of LXT to make it clear which
dumper you are using.
Handle arithmetic right shift during compile time. This comes
up with both the operands are constant expressions. the compiler
is able to evaluate this down to a constant to replace the
expression.
Signed-off-by: Stephen Williams <[email protected]>
Here are some more array fixes. They are mostly better error messages
instead of just asserting and some code cleanup. The one new thing
that probably should have been a separate submission is that down
indexed part select [base -: width] can now be a lvalue.
This patch fixes/enhances the array part select code. It also
verifies that any lval array index in a continuous assignment
is a constant value. Also, %set/av now uses index register 1 as
described in the documentation (as a bit offset).
@* was only expanding to input nets. nex_input() for blocks was removing
any output net that was also an input. There was also a bug in how output
nets were removed. Only outputs currently defined were removed from the
input list.
always @(*) begin
y = a;
z = y;
end
would report "a" as an input. While
always @(*) begin
z = y;
y = a;
end
would report both "a" and "y" as inputs.
To fix this all nex_inputs now take a flag that when true (the default)
correctly removes any output from the input list. Both the above cases
will now return "a". If the flag is false outputs which are also inputs
will be included in the input list. This is what the @* elaboration code
uses to get the correct sensitivity list.
Add/rework VPI access to modpaths. This allows VPI code access to
paths described in specify blocks. In the process, the VPI structure
has been reworked to conform to the IEEE1364 standard.
Signed-off-by: Stephen Williams <[email protected]>
Cleanup klunky implementation of vpi_get/put_delays for modpath
objects. Remove some useless members.
Signed-off-by: Stephen Williams <[email protected]>
Wide division/modulus (more bits than unsigned long) gave incorrect
results when both the divisor and dividend where the same. They also
did not produce an error message when dividing by zero.
This patch enhances the current fflush implementation to flush a mcd or an
individual fd. Before it always flushed everything. A compiletf routine was
also added.
The modpath source node defines the modpath object, and carries the
nodes for the source expression. The modpath outputs are references
by pointers to the vpiModPath that is not in itself a vpi object
any more. This makes the VPI view of a module path look like the
source-destinaiton pair that is the IEEE1364 description of the
modpath.
Add vvp support for modpath path term outputs. This also introduces
the concept of path terms and moves towards the path term in general
for getting at the endpoits of a modpath.
Modpaths need to be in the proper scope in order to be available to
vpi functions. The code generator manages that by writing the modpath
records with scope switch functions. Batch the modpath records at the
end of the structural stuff so that the scope switching doesn't cause
trouble.
Also seperate the modpath code into its own source file.
Signed-off-by: Stephen Williams <[email protected]>
Delay paths need a scope. This helps the code generators bind the
modpaths to the correct scope. This patch doesn't actually make use
of the information, it just makes it available to code generators.
Signed-off-by: Stephen Williams <[email protected]>
Clean up rather poorly written modpath vpi support, fixing the
parse of the modpath syntax element to not use pointless globals.
Collect the modpath code into the delay.cc file instead of the
inapropriate vpi_signal.cc source file.
Signed-off-by: Stephen Williams <[email protected]>
The << operator may not be defined when the RHS is greater than or
equal to the LHS width. To work around the problem the mask is
incrementally generated.
There have been reports in the field of number-to-real conversions
doing bad things with the calculated mantissa. This patch eliminates
a opssible portability problem by reworking the negating of negative
mantissa values.
Signed-off-by: Stephen Williams <[email protected]>
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
The attached patch add an implementation for $dumplimit(). It does
not do a hard limit to the file size, but for VCD files it completes
the current time step and puts a comment in the file. For lxt and
lxt2 files the functionality is in place, but because of buffering
the file can be slightly larger than expected.
Factor common code for processing signed constants to be padded.
In the process, fix some minor bugs in the padding decisions.
Signed-off-by: Stephen Williams <[email protected]>
Fixed some signed/unsigned warnings, including one that caused an
actual runtime error if not dealt with safely.
Signed-off-by: Stephen Williams <[email protected]>
The argument to $unsigned is self-determined no matter what the
context the $unsigned itself is in. This is important only where
the result can be negative but the result width is context-determined.
Do ocntext fitting manually to prevent the context fitting it and
affecting the expression argument.
Signed-off-by: Stephen Williams <[email protected]>
This patch implements the System Verilog $urandom() and $urandom_range()
functions. There are no check to verify that $urandom_range is only given
unsigned arguments. If you give it a negative value the bit pattern will
be interpreted as a unsigned number.
Fix the handling of expressions that have unsized integers and are
in self determined context. Unsized integers are generally assumed
to have at least 32bits.
Signed-off-by: Stephen Williams <[email protected]>
Constant propagation incorrectly elided an entire constant net node
if only the LSB of the driven vector was HiZ. This caused the entire
vector to look like HiZ. Also, the code generator for writing the
constant values missed bits.
Signed-off-by: Stephen Williams <[email protected]>
signed compare in proceedural code was comparing the absolute
value if both operands were negative. Wrong!
Signed-off-by: Stephen Williams <[email protected]>
Implement compare-immediate instructions and generate code to use
these new instructions to improve runtime performance.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds the ability to call command files from other command
files. There is currently a limit of 16 total levels deep (15 stored
plus the current file). -f is now an alias for -c for both the command
line and command files. The parser also reports errors when they occur
along with the file name and line number to aid in debugging problems.
In expressions, user defined functions have a clearly defined
width and the test_width expression needs to express that. Note
that the $signed/$unsigned functions are special and magical.
Signed-off-by: Stephen Williams <[email protected]>
Variable word addresses are not to be adjusted by the bit select
of the vector direction. That is a holdover from when arrays were
stored as bit vectors.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds ivl_scope_time_precision() to the compiler which can
be used to extract the local scope precision. tgt-stub and tgt-vvp
have been modified to use this new function and output a value that
is appropriate. The vvp runtime has been altered to use this new
data which is accessed with the vpip_time_precision_from_handle()
function. vpiTimePrecision uses this function to return the correct
precision.
The outputs to bufif and nmos/pmos devices are always strength-aware,
so should have their outputs connected to a net8 device.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds min_typ_max to expressions. Remember when using a
min_typ_max triplet in an expression they must be enclosed with
parenthesis (1364-2001 section 4.3 page 58).
Add support for accessing the modpath nodes via PLI,
and add support for the vpi_set_delays and vpi_put_delays
functions to set the delays on those paths.
- GSoC 2007
It is legal in Verilog to bind expressions to ports that do not
match the port width. Icarus Verilog needs to create the necessary
part selects to get the connections right.
Signed-off-by: Stephen Williams <[email protected]>
Add code to handle all the primitives currently defined and
fixed a power of ten error in the time units display (it is
either 10^{units} or 1e{units}, but not 10e{units}).
This patch adds functionality to verify that primitives are given
an appropriate number of ports. For multiple output gates (but,
not, pulldown, pullup) it also reports that Icarus currently does
not support multiple outputs when more than one is given.
When a repeat concatenation expression is translated to a netlist,
get the repeat expression right. This comes up when an elab_and_eval
elaboration contains a repeat concationation, and the expression is
ultimately turned into a netlist by expr_synth.
Signed-off-by: Stephen Williams <[email protected]>
Signed divide of 32bit values can overflow if done in a 32bit long
due to the truncation of sign bits. So use the large value algorithm
if the values are >= 31 bits (63 bits on 64bit machines).
Signed-off-by: Stephen Williams <[email protected]>
This patch adds checks to verify that functions do not invoke
statements that are invalid for them (#, @, wait, enable/call
tasks and non blocking assignment). For reference see section
10.3.4 of 1364-2001.
C style comments were not recognized as comments in false or
suppressed sections of ifdef/etc. blocks. This prohibited an
unneeded endif/else/etc. from being commented out with this
style of comment.
I decided not to delete these since we may at some point in time want
this functionality back. For now they are commented out with an
explanation so we know what is going on.
This patch splits the end of compile and the start of simulation call
backs code into two different procedures. The end of compile events are
still executed at the same time they alway were. The start of simulation
events are now run after initialization.
The event loop used to check for $finish at every iteration. This patch
alters this behavior to only check just before you advance to the next
time step. This allows events for the current time step to complete.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
Modified the code that deals with real variables to accept an integer
value when using vpi_put_value(). Also added some type of diagnostic
message for all switch defaults that have an assert(0) to indicate an
error condition, removed CVS comments and removed a small section of
unreachable code.
Previously list of port declarations were considered a complete
definition of the port. This caused problems for some, so this patch
allows implicitly defined ports (no wire/reg/etc.) to have net
declarations in the body.
This would have never been a problem with the actual circuit generated.
The problem was that the assert was checking values that had never been
set. The constructor now explicitly sets these values to zero and while
I was at it I added a couple more asserts.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.
When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).
The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
It is possible for the compiler to generate logic gates that have
inputs from part select nodes. This implements the part select
input methods.
Signed-off-by: Stephen Williams <[email protected]>
This patch fixes an incorrect optimization that was skipping a
call to set the port width when there was no width (a scalar).
The problem with this is that since a (0,0) pair was not added
to the list, later when the width was define to (1,0) the checking
code did not have the (0,0) to tell that there was a mismatch in
the port size. Section 12.3.3 States that the two sizes shall be
identical, so yes this is an error even though it is very minor.
This patch makes vpiFullName for real variables return the correct
value. A Scope reference was added to the base structure along with
the relevant code to support generating the full name. A couple of
memory leaks were plugged and some formatting fixed as well.
It appears that other simulators allow the second argument to
vpi_handle_by_name to be either a scope or a module. Allowing
a module in addition to a scope significantly increases the
usability of this function.
vpi_get_str() can now return a reasonable value for most of the
types used in vvp. I'm not certain I got all of them, but they
are easy to add if any are missing. I also fixed a couple of
typos that I found while looking for all the different types.
Real value constants have width 1 in Icarus Verilog. This is not
the same as the output from $bitstoreal, which is *not* a real
valued expression but a logic vector that losslessly carries the
real value.
Also remove unused CVS markings.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds the missing vpiFullName property to binary and
string parameters (FYI real parameters are not currently supported
by the VPI interface).
This patch implements the swrite* and sformat system tasks. It also
makes $simtime distinguishable from the other integer time tasks.
This was needed to get the correct time units when $simtime was given
as an argument to $swrite*. The string constant code was also modified
to allow a string to be returned as a vector (0/1 bit pattern).
Here are some more specifics about the swrite* changes.
1. They do not share formatting code with the other display functions,
so they may/will produce different results.
2. All %{alpha} codes allow a width and justification. Others have been
enhanced (%t allows the default width and precision to be overridden,
time functions print with time formatting, better error checking and
messages, etc.).
3. %u and %z formatting codes have been added. It is important to note
that these two formats can produce embedded NULLs, since these
functions are returning a string anything after the first NULL will
not be reachable! memcpy is used instead of regular string processing
where needed so that the original string will contain the total
result. The size returned when the string is created is the true
length. A warning will be printed if a string with embedded NULLs is
produced (strlen() does not match the true length).
4. Real numbers are printed with %g instead of %f.
Once this new formatting code has been evaluated we should incorporate
the changes/fixes into the formatting code for the other functions or
the other functions could be modified to use this new code. The true
string length is available so we should be able to work around the
embedded NULL problem.
The calculated return value for the calculated strength value of
a net was left dangling. This patch fixes that. See pr1770199 in
the regression test suite.
Signed-off-by: Stephen Williams <[email protected]>
distinguish between self-determined and value-preserving when
evaluating constants that are arguments to concatenations.
Signed-off-by: Stephen Williams <[email protected]>
Support initialization assignments of real value variables. In the
process, clean up the processing of real variable declarations in
the parser.
Signed-off-by: Stephen Williams <[email protected]>
The standard states that the seed for the random functions should be
an integer/time variable or a register. This patch fixes the compiletf
routines to check for this. There is also a small patch to
vvp/vpi_signal.cc that removes an assert that was failing and replaces
it with appropriate code. The assert was verifying that the source was
not bigger than an integer. The problem with this is that a time
variable or register may be bigger than an integer. I altered the code
to remove the assert and copy only the lower (8 * sizeof integer) bits.
The potential overflow/loss of precision is not checked. This passes
the regression tests.
Delat the compiletf calls until after all the label references
are resolved and link bindings are complete. Otherwise, there may
be dangling references.
Signed-off-by: Stephen Williams <[email protected]>
This patch adds a compiletf routine to the $deposit system task and
simplifies the calltf routine. It also patches the constant string code
to return an appropriate integer value when needed. A number of compiletf
routines that check for this can now be simplified since this (string
constants) no longer causes an assert in an integer environment.
Better handle cases where the scope part of a heirarchical name does
not match any existing scope, or where scope index expressions are
not correct.
Signed-off-by: Stephen Williams <[email protected]>
In rare cases, the reduction logic nodes may get vector part inputs.
This patch adds support for vector parts entering a reduction node.
Signed-off-by: Stephen Williams <[email protected]>
This fixes r-value type references to memory words for memories
that have a non-zero base address. Elaborate the expression
needed to get the canonical word index.
The port input count assertion was triggering incorrectly. It was
comparing the count with the bytes instead of bits in a word.
Signed-off-by: Stephen Williams <[email protected]>
The argument passed to $finish and $stop is not currently used, but it
is now passed down to the functions that may someday do something
useful with it (schedule_finish() and schedule_stop() in vvp/schedule.cc).
Add the missing probabilistic functions and add compiletf routines
for all the functions. The original calltf routines have been
modified as appropriate. The base functions are straight copies
from the standard. I have visually verified the curves with 5,000
points and they look correct.
Even though vpiFinish does not currently do anything with it's
argument I thought it would be best to have them all be in the
correct range [0, 1, 2], so they have been updated as appropriate.
Handle real valued expressions in vector declarations. Also clean
up the handling of vector declaration expressions.
Signed-off-by: Stephen Williams <[email protected]>
Nil parameter overrides can turn up in positional paramter override
lists, where items are intentionally skipped.
Signed-off-by: Stephen Williams <[email protected]>
Be careful to include bitwise differences in double values, because
it is the bit pattern we are passing aroung, not the arithmetic value.
Signed-off-by: Stephen Williams <[email protected]>
The runtime is a vvp runtime engine debug aid that allows for
detailed dump into a debug log. The trace is enabled by setting
the VVP_DEBUG variable and activating specific debug messages
in the vvp source.
Signed-off-by: Stephen Williams <[email protected]>
Make varable drivers (reg vectors and real) propagate their initial
values using a special init scheduler queue. This causes the net to
be loaded with reasonable initial values.
Signed-off-by: Stephen Williams <[email protected]>
Non-constant indexed part select in continuous assignment generates
a select node with the correct width. In the process factor out and
share some of the part select calculations with expr part select
handling methods.
Signed-off-by: Stephen Williams <[email protected]>
Words of net arrays were incorrectly added to the scope. They should
only be attached to the array, and accessed as a word of the array.
Signed-off-by: Stephen Williams <[email protected]>
Real value are vector width of 1, fix real literal to reflect this.
fix leaking real registers in code generation for function arguments.
Load of signal should handle conversion from real to vector. Function
arguments, type vector passed a real value, are an example where this
comes up.
Signed-off-by: Stephen Williams <[email protected]>
Backslash-escapes are processed early, during elaboration, so that
escaped characters show up in all places with the calculated value.
This means the $display formatting will get processed strings and
should not process back-slashes again.
Signed-off-by: Stephen Williams <[email protected]>
Parameter expressions that do not otherwise have a size should
evaluate expressions losslessly, expanding as necessary to prevent
overflow of data.
Signed-off-by: Stephen Williams <[email protected]>
Arrays of nets that have all their words collapsed together can become
a collapsed array as a whole. Add support for this case in the vvp code
generator and runtime.
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
including assing, cassign and force.
Generate NetConcat devices for gate outputs that feed into a
vector results. Use this to hande gate arrays. Also let gate
arrays handle vectors of gates when the outputs allow for it.
Add a vvp_event_anyedge class to handle the special
case of .event statements of edge type. This also
frees the posedge/negedge types to handle all 4 inputs.
Implement table functor recv_vec4 method to receive
and process vectors.
2) adds acc_compare_handle, acc_fetch_range, acc_next_scope and
tf_isetrealdelay, acc_handle_scope
3) makes acc_next reentrant
4) adds basic vpiWire type support
5) fills in some acc_object_of_type() and acc_fetch_{full}type()
6) add vpiLeftRange/RigthRange to signals
as well as a user specified log file, set log
file to buffer lines.
Add vpi_flush function, and clear up some cunfused
return codes from other vpi functions.
Adjust $display and vcd/lxt messages to use the
standard output/log file.
acc_ functions. Add support for standard ACC
string handling.
Add the _pli_types.h header file to carry the
IEEE1364-2001 standard PLI type declarations.
scaled to the local units. Change the internal
implementation of vpiSystemTime the $time functions
to properly account for this. Also add $simtime
to get the simulation time.
length checks for *_get_str() buffers,
temporary buffers for *_get_str() data,
dynamic storage for vpi_get_data() in memory types
shared with signal white space
syntax. Hook this support into existing $attribute
handling, and add number and void value types.
Add to the ivl_target API new functions for access
of complex attributes attached to gates.
instead of link into the netlist. This is faster
and uses less space. Make the NetAssignNB carry
the delays instead of the NetAssign_ lval objects.
Change the vvp code generator to support multiple
l-values, i.e. concatenations of part selects.
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