Generate code for 8:1 muxes msing F5 and F6 muxes.
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steve
parent
327c8826f4
commit
9f1ce170e6
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.14 2002/09/14 05:19:19 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.15 2002/09/15 21:52:19 steve Exp $"
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#endif
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# include "device.h"
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@ -54,6 +54,9 @@
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*
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* MUXCY_L LO, S, DI, CI
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*
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* MUXF5 O, S, I0, I1
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* MUXF6 O, S, I0, I1
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*
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* XORCY O, LI, CI
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*/
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@ -137,9 +140,25 @@ static const char*virtex_library_text =
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port LO (direction OUTPUT))\n"
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" (port S (direction INPUT))\n"
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" (port S (direction INPUT))\n"
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" (port DI (direction INPUT))\n"
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" (port CI (direction INPUT)))))\n"
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" (cell MUXF5 (cellType GENERIC)\n"
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" (view net\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port S (direction INPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell MUXF6 (cellType GENERIC)\n"
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" (view net\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port S (direction INPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell OBUF (cellType GENERIC)\n"
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" (view net\n"
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" (viewType NETLIST)\n"
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@ -952,8 +971,7 @@ static void edif_show_virtex_muxs2(ivl_lpm_t net)
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fprintf(xnf, "(instance (rename U%uF \"%s\")"
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" (viewRef net"
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" (cellRef MUXF5 (libraryRef VIRTEX)))"
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" (property INIT (string \"CA\")))\n",
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" (cellRef MUXF5 (libraryRef VIRTEX))))\n",
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edif_uref, tmp_name);
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fprintf(xnf, "(net U%uAF (joined"
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@ -990,6 +1008,133 @@ static void edif_show_virtex_muxs2(ivl_lpm_t net)
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edif_set_nexus_joint(ivl_lpm_q(net, idx), tmp_name);
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}
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}
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static void edif_show_virtex_muxs3(ivl_lpm_t net)
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{
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unsigned idx;
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assert(ivl_lpm_width(net) >= 1);
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assert(ivl_lpm_selects(net) == 3);
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
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char tmp_name[1024];
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edif_uref += 1;
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sprintf(tmp_name, "%s<%u>", ivl_lpm_name(net), idx);
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fprintf(xnf, "(instance U%uAA"
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" (viewRef net"
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" (cellRef LUT3 (libraryRef VIRTEX)))"
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" (property INIT (string \"CA\")))\n", edif_uref);
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fprintf(xnf, "(instance U%uBA"
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" (viewRef net"
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" (cellRef LUT3 (libraryRef VIRTEX)))"
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" (property INIT (string \"CA\")))\n", edif_uref);
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fprintf(xnf, "(instance U%uFA"
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" (viewRef net"
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" (cellRef MUXF5 (libraryRef VIRTEX))))\n",
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edif_uref);
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fprintf(xnf, "(net U%uAFA (joined"
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" (portRef O (instanceRef U%uAA))"
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" (portRef I0 (instanceRef U%uFA))))\n",
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edif_uref, edif_uref, edif_uref);
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fprintf(xnf, "(net U%uBFA (joined"
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" (portRef O (instanceRef U%uBA))"
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" (portRef I1 (instanceRef U%uFA))))\n",
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edif_uref, edif_uref, edif_uref);
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fprintf(xnf, "(instance U%uAB"
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" (viewRef net"
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" (cellRef LUT3 (libraryRef VIRTEX)))"
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" (property INIT (string \"CA\")))\n", edif_uref);
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fprintf(xnf, "(instance U%uBB"
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" (viewRef net"
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" (cellRef LUT3 (libraryRef VIRTEX)))"
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" (property INIT (string \"CA\")))\n", edif_uref);
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fprintf(xnf, "(instance U%uFB"
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" (viewRef net"
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" (cellRef MUXF5 (libraryRef VIRTEX))))\n",
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edif_uref);
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fprintf(xnf, "(net U%uAFB (joined"
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" (portRef O (instanceRef U%uAB))"
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" (portRef I0 (instanceRef U%uFB))))\n",
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edif_uref, edif_uref, edif_uref);
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fprintf(xnf, "(net U%uBFB (joined"
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" (portRef O (instanceRef U%uBB))"
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" (portRef I1 (instanceRef U%uFB))))\n",
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edif_uref, edif_uref, edif_uref);
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/* Connect the two MUXF5 devices to the MUXF6. */
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fprintf(xnf, "(instance (rename U%uF \"%s\")"
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" (viewRef net"
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" (cellRef MUXF6 (libraryRef VIRTEX))))\n",
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edif_uref, tmp_name);
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fprintf(xnf, "(net U%uFA (joined"
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" (portRef O (instanceRef U%uFA))"
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" (portRef I0 (instanceRef U%uF))))\n",
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edif_uref, edif_uref, edif_uref);
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fprintf(xnf, "(net U%uFB (joined"
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" (portRef O (instanceRef U%uFB))"
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" (portRef I1 (instanceRef U%uF))))\n",
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edif_uref, edif_uref, edif_uref);
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sprintf(tmp_name, "(portRef I0 (instanceRef U%uAA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 0, idx), tmp_name);
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sprintf(tmp_name, "(portRef I1 (instanceRef U%uAA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 1, idx), tmp_name);
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sprintf(tmp_name, "(portRef I0 (instanceRef U%uBA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 2, idx), tmp_name);
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sprintf(tmp_name, "(portRef I1 (instanceRef U%uBA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 3, idx), tmp_name);
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sprintf(tmp_name, "(portRef I0 (instanceRef U%uAB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 4, idx), tmp_name);
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sprintf(tmp_name, "(portRef I1 (instanceRef U%uAB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 5, idx), tmp_name);
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sprintf(tmp_name, "(portRef I0 (instanceRef U%uBB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 6, idx), tmp_name);
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sprintf(tmp_name, "(portRef I1 (instanceRef U%uBB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_data2(net, 7, idx), tmp_name);
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sprintf(tmp_name, "(portRef I2 (instanceRef U%uAA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 0), tmp_name);
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sprintf(tmp_name, "(portRef I2 (instanceRef U%uBA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 0), tmp_name);
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sprintf(tmp_name, "(portRef I2 (instanceRef U%uAB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 0), tmp_name);
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sprintf(tmp_name, "(portRef I2 (instanceRef U%uBB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 0), tmp_name);
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sprintf(tmp_name, "(portRef S (instanceRef U%uFA))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 1), tmp_name);
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sprintf(tmp_name, "(portRef S (instanceRef U%uFB))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 1), tmp_name);
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sprintf(tmp_name, "(portRef S (instanceRef U%uF))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_select(net, 2), tmp_name);
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sprintf(tmp_name, "(portRef O (instanceRef U%uF))", edif_uref);
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edif_set_nexus_joint(ivl_lpm_q(net, idx), tmp_name);
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}
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}
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static void edif_show_virtex_mux(ivl_lpm_t net)
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{
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@ -1000,6 +1145,9 @@ static void edif_show_virtex_mux(ivl_lpm_t net)
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case 2:
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edif_show_virtex_muxs2(net);
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break;
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case 3:
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edif_show_virtex_muxs3(net);
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break;
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default:
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assert(0);
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break;
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@ -1149,6 +1297,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.15 2002/09/15 21:52:19 steve
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* Generate code for 8:1 muxes msing F5 and F6 muxes.
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*
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* Revision 1.14 2002/09/14 05:19:19 steve
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* Generate Virtex code for 4:1 mux slices.
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*
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