Move library cell management to common file.
This commit is contained in:
steve
parent
15fa7246f2
commit
aad7816949
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.8 2003/03/24 00:47:54 steve Exp $"
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#ident "$Id: Makefile.in,v 1.9 2003/04/05 05:53:34 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -53,7 +53,7 @@ dep:
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mv $*.d dep
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D = d-generic.o d-generic-edif.o d-virtex.o d-virtex2.o
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O = edif.o fpga.o gates.o mangle.o tables.o $D
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O = edif.o fpga.o gates.o mangle.o tables.o xilinx.o $D
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ifeq (@WIN32@,yes)
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TGTLDFLAGS=-L.. -livl
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@ -17,12 +17,13 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.9 2003/04/05 01:35:40 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.10 2003/04/05 05:53:34 steve Exp $"
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#endif
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# include "device.h"
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# include "fpga_priv.h"
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# include "edif.h"
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# include "xilinx.h"
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# include <stdlib.h>
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# include <string.h>
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#ifdef HAVE_MALLOC_H
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@ -45,217 +46,13 @@ static edif_xlibrary_t xlib = 0;
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static edif_cell_t cell_0 = 0;
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static edif_cell_t cell_1 = 0;
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static edif_cell_t cell_fdce = 0;
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static edif_cell_t cell_fdcpe = 0;
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const unsigned FDCE_Q = 0;
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const unsigned FDCE_C = 1;
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const unsigned FDCE_D = 2;
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const unsigned FDCE_CE = 3;
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const unsigned FDCE_CLR = 4;
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const unsigned FDCE_PRE = 5;
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static edif_cell_t cell_ipad = 0;
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static edif_cell_t cell_opad = 0;
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static edif_cell_t cell_buf = 0;
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static edif_cell_t cell_inv = 0;
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static edif_cell_t cell_ibuf = 0;
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static edif_cell_t cell_obuf = 0;
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const unsigned BUF_O = 0;
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const unsigned BUF_I = 1;
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static edif_cell_t cell_lut2 = 0;
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static edif_cell_t cell_lut3 = 0;
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static edif_cell_t cell_lut4 = 0;
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const unsigned LUT_O = 0;
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const unsigned LUT_I0 = 1;
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const unsigned LUT_I1 = 2;
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const unsigned LUT_I2 = 3;
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const unsigned LUT_I3 = 4;
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static edif_cell_t cell_muxcy = 0;
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static edif_cell_t cell_muxcy_l = 0;
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const unsigned MUXCY_O = 0;
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const unsigned MUXCY_DI = 1;
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const unsigned MUXCY_CI = 2;
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const unsigned MUXCY_S = 3;
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static edif_cell_t cell_xorcy = 0;
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const unsigned XORCY_O = 0;
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const unsigned XORCY_CI = 1;
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const unsigned XORCY_LI = 2;
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/*
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* The check_cell_* functions can be called in front of any reference
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* to the matching cell_* variable to make sure the cell type has been
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* created. By creating the cell type only when it is needed, we
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* reduce the size of the library declaration, and also better support
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* cross-family code sharing.
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*/
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static void check_cell_fdce(void)
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{
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if (cell_fdce != 0)
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return;
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cell_fdce = edif_xcell_create(xlib, "FDCE", 5);
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edif_cell_portconfig(cell_fdce, FDCE_Q, "Q", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdce, FDCE_D, "D", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_fdce, FDCE_C, "C", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdce, FDCE_CE, "CE", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdce, FDCE_CLR,"CLR", IVL_SIP_INPUT);
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}
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static void check_cell_fdcpe(void)
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{
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if (cell_fdcpe != 0)
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return;
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cell_fdcpe = edif_xcell_create(xlib, "FDCPE", 6);
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edif_cell_portconfig(cell_fdcpe, FDCE_Q, "Q", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdcpe, FDCE_D, "D", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_fdcpe, FDCE_C, "C", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdcpe, FDCE_CE, "CE", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdcpe, FDCE_CLR,"CLR", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_fdcpe, FDCE_PRE,"PRE", IVL_SIP_INPUT);
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}
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static void check_cell_buf(void)
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{
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if (cell_buf != 0)
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return;
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cell_buf = edif_xcell_create(xlib, "BUF", 2);
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edif_cell_portconfig(cell_buf, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_buf, BUF_I, "I", IVL_SIP_INPUT);
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}
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static void check_cell_inv(void)
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{
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if (cell_inv != 0)
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return;
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cell_inv = edif_xcell_create(xlib, "INV", 2);
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edif_cell_portconfig(cell_inv, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_inv, BUF_I, "I", IVL_SIP_INPUT);
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}
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static void check_cell_ibuf(void)
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{
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if (cell_ibuf != 0)
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return;
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cell_ibuf = edif_xcell_create(xlib, "IBUF", 2);
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edif_cell_portconfig(cell_ibuf, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_ibuf, BUF_I, "I", IVL_SIP_INPUT);
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}
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static void check_cell_obuf(void)
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{
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if (cell_obuf != 0)
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return;
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cell_obuf = edif_xcell_create(xlib, "OBUF", 2);
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edif_cell_portconfig(cell_obuf, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_obuf, BUF_I, "I", IVL_SIP_INPUT);
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}
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static void check_cell_lut2(void)
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{
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if (cell_lut2 != 0)
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return;
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cell_lut2 = edif_xcell_create(xlib, "LUT2", 3);
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edif_cell_portconfig(cell_lut2, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_lut2, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut2, LUT_I1, "I1", IVL_SIP_INPUT);
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}
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static void check_cell_lut3(void)
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{
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if (cell_lut3 != 0)
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return;
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cell_lut3 = edif_xcell_create(xlib, "LUT3", 4);
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edif_cell_portconfig(cell_lut3, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_lut3, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut3, LUT_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut3, LUT_I2, "I2", IVL_SIP_INPUT);
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}
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static void check_cell_lut4(void)
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{
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if (cell_lut4 != 0)
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return;
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cell_lut4 = edif_xcell_create(xlib, "LUT4", 5);
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edif_cell_portconfig(cell_lut4, LUT_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_lut4, LUT_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut4, LUT_I1, "I1", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut4, LUT_I2, "I2", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_lut4, LUT_I3, "I3", IVL_SIP_INPUT);
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}
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static void check_cell_muxcy(void)
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{
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if (cell_muxcy != 0)
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return;
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cell_muxcy = edif_xcell_create(xlib, "MUXCY", 4);
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edif_cell_portconfig(cell_muxcy, MUXCY_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_muxcy, MUXCY_DI, "DI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_muxcy, MUXCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_muxcy, MUXCY_S, "S", IVL_SIP_INPUT);
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}
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static void check_cell_muxcy_l(void)
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{
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if (cell_muxcy_l != 0)
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return;
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cell_muxcy_l = edif_xcell_create(xlib, "MUXCY_L", 4);
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edif_cell_portconfig(cell_muxcy_l, MUXCY_O, "LO", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_muxcy_l, MUXCY_DI, "DI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_muxcy_l, MUXCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_muxcy_l, MUXCY_S, "S", IVL_SIP_INPUT);
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}
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static void check_cell_xorcy(void)
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{
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if (cell_xorcy != 0)
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return;
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cell_xorcy = edif_xcell_create(xlib, "XORCY", 3);
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edif_cell_portconfig(cell_xorcy, XORCY_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell_xorcy, XORCY_CI, "CI", IVL_SIP_INPUT);
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edif_cell_portconfig(cell_xorcy, XORCY_LI, "LI", IVL_SIP_INPUT);
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}
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const unsigned MULT_AND_LO = 0;
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const unsigned MULT_AND_I0 = 1;
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const unsigned MULT_AND_I1 = 2;
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static edif_cell_t celltable_mult_and(edif_xlibrary_t xlib)
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{
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edif_cell_t cell = edif_xcell_create(xlib, "MULT_AND", 3);
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edif_cell_portconfig(cell, MULT_AND_LO, "LO", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, MULT_AND_I0, "I0", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, MULT_AND_I1, "I1", IVL_SIP_INPUT);
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return cell;
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}
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static edif_cell_t celltable_bufg(edif_xlibrary_t xlib)
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{
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edif_cell_t cell = edif_xcell_create(xlib, "BUFG", 2);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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return cell;
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}
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const static struct edif_xlib_celltable virtex2_celltable[] = {
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{ "BUFG", celltable_bufg },
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{ "MULT_AND", celltable_mult_and },
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{ "BUFG", xilinx_cell_bufg },
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{ "MULT_AND", xilinx_cell_mult_and },
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{ 0, 0}
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};
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@ -430,9 +227,8 @@ static void virtex2_pad(ivl_signal_t sig, const char*str)
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switch (ivl_signal_port(sig)) {
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case IVL_SIP_INPUT:
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check_cell_ibuf();
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pad = edif_cellref_create(edf, cell_ipad);
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buf = edif_cellref_create(edf, cell_ibuf);
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buf = edif_cellref_create(edf, xilinx_cell_ibuf(xlib));
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jnt = edif_joint_create(edf);
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edif_joint_rename(jnt, name_str);
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@ -444,9 +240,8 @@ static void virtex2_pad(ivl_signal_t sig, const char*str)
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break;
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case IVL_SIP_OUTPUT:
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check_cell_obuf();
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pad = edif_cellref_create(edf, cell_opad);
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buf = edif_cellref_create(edf, cell_obuf);
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buf = edif_cellref_create(edf, xilinx_cell_obuf(xlib));
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jnt = edif_joint_create(edf);
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edif_joint_rename(jnt, name_str);
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@ -521,20 +316,17 @@ static void lut_logic(ivl_net_logic_t net, const char*init3,
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switch (ivl_logic_pins(net)) {
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case 3:
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check_cell_lut2();
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lut = edif_cellref_create(edf, cell_lut2);
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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init = init3;
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break;
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case 4:
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check_cell_lut3();
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lut = edif_cellref_create(edf, cell_lut3);
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lut = edif_cellref_create(edf, xilinx_cell_lut3(xlib));
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init = init4;
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break;
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case 5:
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check_cell_lut4();
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lut = edif_cellref_create(edf, cell_lut4);
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lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
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init = init5;
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break;
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}
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@ -577,9 +369,8 @@ static void virtex2_logic(ivl_net_logic_t net)
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case IVL_LO_BUF:
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case IVL_LO_BUFZ:
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assert(ivl_logic_pins(net) == 2);
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check_cell_buf();
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obj = edif_cellref_create(edf, cell_buf);
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obj = edif_cellref_create(edf, xilinx_cell_buf(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, BUF_O);
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@ -649,11 +440,9 @@ static void virtex2_generic_dff(ivl_lpm_t net)
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/* If there is a preset, then select an FDCPE instead of
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an FDCE device. */
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if (aset && (abits[idx] == '1')) {
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check_cell_fdcpe();
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obj = edif_cellref_create(edf, cell_fdcpe);
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obj = edif_cellref_create(edf, xilinx_cell_fdcpe(xlib));
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} else {
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check_cell_fdce();
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obj = edif_cellref_create(edf, cell_fdce);
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obj = edif_cellref_create(edf, xilinx_cell_fdce(xlib));
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}
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, idx));
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@ -706,9 +495,6 @@ static void virtex2_show_shiftl(ivl_lpm_t net)
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edif_joint_t pad0;
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check_cell_lut3();
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check_cell_lut4();
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/* First, find out how many select inputs we really need. We
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can only use the selects that are enough to shift out the
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entire width of the device. The excess can be used as an
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@ -756,10 +542,10 @@ static void virtex2_show_shiftl(ivl_lpm_t net)
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edif_cell_t lut;
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if (((sdx+1) == nsel) && (nsel < ivl_lpm_selects(net))) {
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lut = cell_lut4;
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lut = xilinx_cell_lut4(xlib);
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init_string = "00CA";
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} else {
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lut = cell_lut3;
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lut = xilinx_cell_lut3(xlib);
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init_string = "CA";
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}
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@ -884,8 +670,7 @@ static void virtex2_add(ivl_lpm_t net)
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then it is an XNOR. */
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if (ivl_lpm_width(net) == 1) {
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check_cell_lut2();
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lut = edif_cellref_create(edf, cell_lut2);
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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@ -902,13 +687,9 @@ static void virtex2_add(ivl_lpm_t net)
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assert(ivl_lpm_width(net) > 1);
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check_cell_lut2();
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check_cell_xorcy();
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check_cell_muxcy_l();
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lut = edif_cellref_create(edf, cell_lut2);
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xorcy = edif_cellref_create(edf, cell_xorcy);
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muxcy = edif_cellref_create(edf, cell_muxcy_l);
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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xorcy = edif_cellref_create(edf, xilinx_cell_xorcy(xlib));
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muxcy = edif_cellref_create(edf, xilinx_cell_muxcy_l(xlib));
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edif_cellref_pstring(lut, "INIT", ha_init);
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/* The bottom carry-in takes a constant that primes the add or
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@ -949,15 +730,15 @@ static void virtex2_add(ivl_lpm_t net)
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for (idx = 1 ; idx < ivl_lpm_width(net) ; idx += 1) {
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edif_cellref_t muxcy0 = muxcy;
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lut = edif_cellref_create(edf, cell_lut2);
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xorcy = edif_cellref_create(edf, cell_xorcy);
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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xorcy = edif_cellref_create(edf, xilinx_cell_xorcy(xlib));
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edif_cellref_pstring(lut, "INIT", ha_init);
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/* If this is the last bit, then there is no further
|
||||
propagation in the carry chain, and I can skip the
|
||||
carry mux MUXCY. */
|
||||
if ((idx+1) < ivl_lpm_width(net))
|
||||
muxcy = edif_cellref_create(edf, cell_muxcy_l);
|
||||
muxcy = edif_cellref_create(edf, xilinx_cell_muxcy_l(xlib));
|
||||
else
|
||||
muxcy = 0;
|
||||
|
||||
|
|
@ -1038,8 +819,7 @@ static void virtex_eq(ivl_lpm_t net)
|
|||
switch (ivl_lpm_width(net)) {
|
||||
|
||||
case 1:
|
||||
check_cell_lut2();
|
||||
lut = edif_cellref_create(edf, cell_lut2);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", eq? "9" : "6");
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
|
||||
|
|
@ -1053,8 +833,7 @@ static void virtex_eq(ivl_lpm_t net)
|
|||
return;
|
||||
|
||||
case 2:
|
||||
check_cell_lut4();
|
||||
lut = edif_cellref_create(edf, cell_lut4);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", eq? "9009" : "6FF6");
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
|
||||
|
|
@ -1074,10 +853,6 @@ static void virtex_eq(ivl_lpm_t net)
|
|||
return;
|
||||
|
||||
default:
|
||||
check_cell_lut2();
|
||||
check_cell_lut4();
|
||||
check_cell_muxcy();
|
||||
|
||||
{ edif_cellref_t di;
|
||||
di = edif_cellref_create(edf, eq? cell_0 : cell_1);
|
||||
jnt_di = edif_joint_create(edf);
|
||||
|
|
@ -1090,12 +865,12 @@ static void virtex_eq(ivl_lpm_t net)
|
|||
if ((idx + 1) == ivl_lpm_width(net))
|
||||
subwid = 1;
|
||||
|
||||
mux = edif_cellref_create(edf, cell_muxcy);
|
||||
mux = edif_cellref_create(edf, xilinx_cell_muxcy(xlib));
|
||||
if (subwid == 2) {
|
||||
lut = edif_cellref_create(edf, cell_lut4);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", "9009");
|
||||
} else {
|
||||
lut = edif_cellref_create(edf, cell_lut2);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", "9");
|
||||
}
|
||||
|
||||
|
|
@ -1168,8 +943,7 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
|
|||
|
||||
Connect the A value to I1 and the B value to I0. */
|
||||
|
||||
check_cell_lut2();
|
||||
lut = edif_cellref_create(edf, cell_lut2);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", "D");
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
|
||||
|
|
@ -1206,9 +980,8 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
|
|||
The I3-I0 inputs are A1 A0 B1 B0 in that order. */
|
||||
|
||||
assert(ivl_lpm_width(net) >= 2);
|
||||
check_cell_lut4();
|
||||
|
||||
lut = edif_cellref_create(edf, cell_lut4);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut4(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", "F731");
|
||||
|
||||
jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
|
||||
|
|
@ -1257,11 +1030,8 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
|
|||
output of the LUT4 device for the least significant bits,
|
||||
and use that to generate the initial CI for the chain. */
|
||||
|
||||
check_cell_lut2();
|
||||
check_cell_muxcy();
|
||||
check_cell_muxcy_l();
|
||||
|
||||
muxcy_prev = edif_cellref_create(edf, cell_muxcy_l);
|
||||
muxcy_prev = edif_cellref_create(edf, xilinx_cell_muxcy_l(xlib));
|
||||
jnt = edif_joint_create(edf);
|
||||
|
||||
edif_add_to_joint(jnt, lut, LUT_O);
|
||||
|
|
@ -1281,8 +1051,8 @@ static void virtex2_cmp_ge(ivl_lpm_t net)
|
|||
for (idx = 2 ; idx < ivl_lpm_width(net) ; idx += 1) {
|
||||
edif_cellref_t muxcy;
|
||||
|
||||
lut = edif_cellref_create(edf, cell_lut2);
|
||||
muxcy = edif_cellref_create(edf, cell_muxcy);
|
||||
lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
|
||||
muxcy = edif_cellref_create(edf, xilinx_cell_muxcy(xlib));
|
||||
edif_cellref_pstring(lut, "INIT", "9");
|
||||
|
||||
jnt = edif_joint_create(edf);
|
||||
|
|
@ -1326,6 +1096,9 @@ const struct device_s d_virtex2_edif = {
|
|||
|
||||
/*
|
||||
* $Log: d-virtex2.c,v $
|
||||
* Revision 1.10 2003/04/05 05:53:34 steve
|
||||
* Move library cell management to common file.
|
||||
*
|
||||
* Revision 1.9 2003/04/05 01:35:40 steve
|
||||
* Fix LUT function for chained NE.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,209 @@
|
|||
/*
|
||||
* Copyright (c) 2003 Stephen Williams (steve at icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xilinx.c,v 1.1 2003/04/05 05:53:34 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "xilinx.h"
|
||||
|
||||
edif_cell_t xilinx_cell_buf(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "BUF", 2);
|
||||
edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "BUFG", 2);
|
||||
edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "IBUF", 2);
|
||||
edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_inv(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "INV", 2);
|
||||
edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "OBUF", 2);
|
||||
edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
|
||||
edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "LUT2", 3);
|
||||
edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "LUT3", 4);
|
||||
edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "LUT4", 5);
|
||||
edif_cell_portconfig(cell, LUT_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, LUT_I0, "I0", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I1, "I1", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I2, "I2", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, LUT_I3, "I3", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
|
||||
edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "FDCE", 5);
|
||||
edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "FDCPE", 6);
|
||||
edif_cell_portconfig(cell, FDCE_Q, "Q", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_D, "D", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, FDCE_C, "C", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CE, "CE", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_CLR,"CLR", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, FDCE_PRE,"PRE", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
|
||||
edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "MULT_AND", 3);
|
||||
edif_cell_portconfig(cell, MULT_AND_LO, "LO", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, MULT_AND_I0, "I0", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, MULT_AND_I1, "I1", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "MUXCY", 4);
|
||||
edif_cell_portconfig(cell, MUXCY_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_S, "S", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "MUXCY_L", 4);
|
||||
edif_cell_portconfig(cell, MUXCY_O, "LO", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_DI, "DI", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_CI, "CI", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, MUXCY_S, "S", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
|
||||
{
|
||||
static edif_cell_t cell = 0;
|
||||
if (cell != 0) return cell;
|
||||
|
||||
cell = edif_xcell_create(xlib, "XORCY", 3);
|
||||
edif_cell_portconfig(cell, XORCY_O, "O", IVL_SIP_OUTPUT);
|
||||
edif_cell_portconfig(cell, XORCY_CI, "CI", IVL_SIP_INPUT);
|
||||
edif_cell_portconfig(cell, XORCY_LI, "LI", IVL_SIP_INPUT);
|
||||
return cell;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* $Log: xilinx.c,v $
|
||||
* Revision 1.1 2003/04/05 05:53:34 steve
|
||||
* Move library cell management to common file.
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
#ifndef __xilinx_H
|
||||
#define __xilinx_H
|
||||
/*
|
||||
* Copyright (c) 2003 Stephen Williams (steve at icarus.com)
|
||||
*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: xilinx.h,v 1.1 2003/04/05 05:53:34 steve Exp $"
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This header file includes XILINX library support functions. They
|
||||
* manage the creation and reference of cells from the library. Use
|
||||
* the xililx_cell_* functions to get an edif_cell_t from the
|
||||
* library. The function will create the cell in the library if
|
||||
* needed, or will return the existing cell if it was already called.
|
||||
*/
|
||||
# include "edif.h"
|
||||
|
||||
|
||||
/* === BUF Devices === */
|
||||
|
||||
/* Buffer types of devices have the BUF_O and BUF_I pin
|
||||
assignments. The BUF, INV, and certain specialized devices fit in
|
||||
this category. */
|
||||
extern edif_cell_t xilinx_cell_buf (edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_inv (edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib);
|
||||
#define BUF_O 0
|
||||
#define BUF_I 1
|
||||
|
||||
|
||||
/* === LUT Devices === */
|
||||
|
||||
/* Most Xilinx devices have LUT2/3/4 devices that take, respectively,
|
||||
2, 3 or 4 inputs. All forms have a single bit output. Also, the
|
||||
real behavior of the device will need to be specified by an INIT
|
||||
parameter string. */
|
||||
extern edif_cell_t xilinx_cell_lut2(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_lut3(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_lut4(edif_xlibrary_t xlib);
|
||||
#define LUT_O 0
|
||||
#define LUT_I0 1
|
||||
#define LUT_I1 2
|
||||
#define LUT_I2 3
|
||||
#define LUT_I3 4
|
||||
|
||||
|
||||
/* === Flip-Flop Devices === */
|
||||
|
||||
extern edif_cell_t xilinx_cell_fdce(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_fdcpe(edif_xlibrary_t xlib);
|
||||
#define FDCE_Q 0
|
||||
#define FDCE_C 1
|
||||
#define FDCE_D 2
|
||||
#define FDCE_CE 3
|
||||
#define FDCE_CLR 4
|
||||
#define FDCE_PRE 5
|
||||
|
||||
|
||||
/* === Virtex/Virtex2 Carry Chain Logic === */
|
||||
|
||||
extern edif_cell_t xilinx_cell_mult_and(edif_xlibrary_t xlib);
|
||||
#define MULT_AND_LO 0
|
||||
#define MULT_AND_I0 1
|
||||
#define MULT_AND_I1 2
|
||||
|
||||
extern edif_cell_t xilinx_cell_muxcy(edif_xlibrary_t xlib);
|
||||
extern edif_cell_t xilinx_cell_muxcy_l(edif_xlibrary_t xlib);
|
||||
#define MUXCY_O 0
|
||||
#define MUXCY_DI 1
|
||||
#define MUXCY_CI 2
|
||||
#define MUXCY_S 3
|
||||
|
||||
extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
|
||||
#define XORCY_O 0
|
||||
#define XORCY_CI 1
|
||||
#define XORCY_LI 2
|
||||
|
||||
/*
|
||||
* $Log: xilinx.h,v $
|
||||
* Revision 1.1 2003/04/05 05:53:34 steve
|
||||
* Move library cell management to common file.
|
||||
*
|
||||
*/
|
||||
#endif
|
||||
Loading…
Reference in New Issue