Add == and some lut logic.
This commit is contained in:
steve
parent
6495d0bd5d
commit
882c46437c
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.7 2003/04/04 04:59:03 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.8 2003/04/04 06:20:29 steve Exp $"
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#endif
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# include "device.h"
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@ -85,10 +85,6 @@ const unsigned XORCY_O = 0;
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const unsigned XORCY_CI = 1;
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const unsigned XORCY_LI = 2;
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const unsigned MULT_AND_LO = 0;
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const unsigned MULT_AND_I0 = 1;
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const unsigned MULT_AND_I1 = 2;
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/*
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* The check_cell_* functions can be called in front of any reference
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* to the matching cell_* variable to make sure the cell type has been
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@ -236,6 +232,10 @@ static void check_cell_xorcy(void)
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}
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const unsigned MULT_AND_LO = 0;
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const unsigned MULT_AND_I0 = 1;
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const unsigned MULT_AND_I1 = 2;
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static edif_cell_t celltable_mult_and(edif_xlibrary_t xlib)
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{
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edif_cell_t cell = edif_xcell_create(xlib, "MULT_AND", 3);
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@ -509,6 +509,57 @@ static void edif_cellref_logic(ivl_net_logic_t net, const char*def)
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free(str);
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}
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static void lut_logic(ivl_net_logic_t net, const char*init3,
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const char*init4, const char*init5)
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{
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edif_cellref_t lut;
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edif_joint_t jnt;
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const char* init;
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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case 3:
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check_cell_lut2();
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lut = edif_cellref_create(edf, cell_lut2);
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init = init3;
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break;
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case 4:
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check_cell_lut3();
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lut = edif_cellref_create(edf, cell_lut3);
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init = init4;
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break;
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case 5:
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check_cell_lut4();
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lut = edif_cellref_create(edf, cell_lut4);
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init = init5;
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break;
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}
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edif_cellref_pstring(lut, "INIT", init);
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switch (ivl_logic_pins(net)) {
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case 5:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 4));
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edif_add_to_joint(jnt, lut, LUT_I3);
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case 4:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 3));
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edif_add_to_joint(jnt, lut, LUT_I2);
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case 3:
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, lut, LUT_I1);
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}
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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}
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static void virtex2_logic(ivl_net_logic_t net)
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{
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edif_cellref_t obj;
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@ -537,69 +588,34 @@ static void virtex2_logic(ivl_net_logic_t net)
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edif_add_to_joint(jnt, obj, BUF_I);
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break;
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "8", "80", "8000");
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break;
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case IVL_LO_NOR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "1", "01", "0001");
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break;
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case IVL_LO_OR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "E", "FE", "FFFE");
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break;
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switch (ivl_logic_pins(net)) {
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case IVL_LO_XNOR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "9", "69", "9669");
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break;
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case 3:
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check_cell_lut2();
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obj = edif_cellref_create(edf, cell_lut2);
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edif_cellref_pstring(obj, "INIT", "E");
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, obj, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, obj, LUT_I1);
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break;
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case 4:
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check_cell_lut3();
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obj = edif_cellref_create(edf, cell_lut3);
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edif_cellref_pstring(obj, "INIT", "FE");
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, obj, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, obj, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 3));
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edif_add_to_joint(jnt, obj, LUT_I2);
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break;
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case 5:
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check_cell_lut4();
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obj = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(obj, "INIT", "FFFE");
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, obj, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, obj, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 3));
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edif_add_to_joint(jnt, obj, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 4));
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edif_add_to_joint(jnt, obj, LUT_I3);
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break;
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default:
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assert(0);
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}
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case IVL_LO_XOR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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lut_logic(net, "6", "96", "6996");
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break;
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default:
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@ -968,6 +984,162 @@ static void virtex2_add(ivl_lpm_t net)
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}
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/*
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* This method handles both == and != operators, the identity
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* comparison operators.
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*
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* If the identity compare is applied to small enough input vectors,
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* it is shoved into a single LUT. Otherwise, it is strung out into a
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* row of LUT devices chained together by carry muxes. The output of
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* the comparison is the output of the last mux.
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*
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* When the compare is small, a LUT is generated with the appropriate
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* truth table to cause an == or != result.
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*
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* When the compare is too wide for a single LUT, then it is made into
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* a chain connected by a string of carry mux devices. Each LUT
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* implements == for up to two pairs of bits, even if the final output
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* is supposed to be !=. The LUT output is connected to an associated
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* MUX select input. The CO output of each muxcy is passed up to the
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* next higher order bits of the compare.
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*
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* For identity == compare, a != output from the LUT selects the DI
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* input of the muxcy, generating a 0 output that is passed up. Since
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* the next higher muxcy now gets a 0 input to both DI and CI, the
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* output of the next higher muxcy is guaranteed to be 0, and so on to
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* the final output of the carry chain. If the output from a LUT is ==,
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* then the CI input of the muxcy is selected and the truth of this
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* level depends on lower order bits. The least significan muxcy is
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* connected to GND and VCC so that its CO follows the least
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* significant LUT.
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*
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* Identity != is the same as == except that the output is
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* inverted. To get that effect without putting an inverter on the
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* output of the top muxcy pin CO (which would cost a LUT) the DI
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* inputs are all connected to VCC instead of GND, and the CI of the
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* least significant muxcy is connected to GND instead of VCC.
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*/
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static void virtex_eq(ivl_lpm_t net)
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{
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edif_cellref_t lut, mux, mux_prev;
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edif_joint_t jnt, jnt_di;
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unsigned idx;
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/* True if I'm implementing CMP_EQ instead of CMP_NE */
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int eq = 1;
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assert(ivl_lpm_width(net) >= 1);
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if (ivl_lpm_type(net) == IVL_LPM_CMP_NE)
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eq = 0;
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switch (ivl_lpm_width(net)) {
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case 1:
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check_cell_lut2();
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lut = edif_cellref_create(edf, cell_lut2);
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edif_cellref_pstring(lut, "INIT", eq? "9" : "6");
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I1);
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return;
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case 2:
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check_cell_lut4();
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lut = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(lut, "INIT", eq? "9009" : "6FF6");
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, lut, LUT_O);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 0));
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edif_add_to_joint(jnt, lut, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, 1));
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edif_add_to_joint(jnt, lut, LUT_I3);
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return;
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default:
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check_cell_lut2();
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check_cell_lut4();
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check_cell_muxcy();
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{ edif_cellref_t di;
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di = edif_cellref_create(edf, eq? cell_0 : cell_1);
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jnt_di = edif_joint_create(edf);
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edif_add_to_joint(jnt_di, di, 0);
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}
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mux_prev = 0;
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 2) {
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int subwid = 2;
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if ((idx + 1) == ivl_lpm_width(net))
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subwid = 1;
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mux = edif_cellref_create(edf, cell_muxcy);
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if (subwid == 2) {
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lut = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(lut, "INIT", eq? "9009" : "6FF6");
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} else {
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lut = edif_cellref_create(edf, cell_lut2);
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edif_cellref_pstring(lut, "INIT", eq? "9" : "6");
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}
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, mux, MUXCY_S);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_data(net, idx));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_lpm_datab(net, idx));
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edif_add_to_joint(jnt, lut, LUT_I1);
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if (subwid > 1) {
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jnt = edif_joint_of_nexus(edf,
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ivl_lpm_data(net, idx+1));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf,
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ivl_lpm_datab(net, idx+1));
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edif_add_to_joint(jnt, lut, LUT_I3);
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}
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edif_add_to_joint(jnt_di, mux, MUXCY_DI);
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if (mux_prev) {
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, mux, MUXCY_CI);
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edif_add_to_joint(jnt, mux_prev, MUXCY_O);
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} else {
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edif_cellref_t ci;
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ci = edif_cellref_create(edf, eq? cell_1 : cell_0);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, ci, 0);
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edif_add_to_joint(jnt, mux, MUXCY_CI);
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}
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mux_prev = mux;
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}
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jnt = edif_joint_of_nexus(edf, ivl_lpm_q(net, 0));
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edif_add_to_joint(jnt, mux_prev, MUXCY_O);
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return;
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}
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}
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/*
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* Implement hardware for the device (A >= B). We use LUT devices if
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* it can handle the slices, or carry chain logic if the slices must
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@ -1139,8 +1311,8 @@ const struct device_s d_virtex2_edif = {
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virtex2_pad,
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virtex2_logic,
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virtex2_generic_dff,
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0,
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0,
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virtex_eq,
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virtex_eq,
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virtex2_cmp_ge,
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0,
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virtex2_add,
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@ -1152,6 +1324,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.8 2003/04/04 06:20:29 steve
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* Add == and some lut logic.
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*
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* Revision 1.7 2003/04/04 04:59:03 steve
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* Add xlibrary celltable.
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*
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