Do not change reg to wire in NetAssign_ unless synthesizing.
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steve
parent
21ba781604
commit
d76ad25778
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: net_assign.cc,v 1.17 2004/02/18 17:11:56 steve Exp $"
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#ident "$Id: net_assign.cc,v 1.18 2004/08/28 15:08:31 steve Exp $"
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#endif
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# include "config.h"
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@ -67,7 +67,7 @@ NetAssign_::~NetAssign_()
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{
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if (sig_) {
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sig_->decr_lref();
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if (sig_->peek_lref() == 0)
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if (turn_sig_to_wire_on_release_ && sig_->peek_lref() == 0)
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sig_->type(NetNet::WIRE);
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}
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@ -142,6 +142,13 @@ unsigned NetAssign_::get_loff() const
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return loff_;
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}
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/*
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*/
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void NetAssign_::turn_sig_to_wire_on_release()
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{
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turn_sig_to_wire_on_release_ = true;
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}
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NetAssignBase::NetAssignBase(NetAssign_*lv, NetExpr*rv)
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: lval_(lv), rval_(rv), delay_(0)
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{
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@ -254,6 +261,9 @@ NetAssignNB::~NetAssignNB()
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/*
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* $Log: net_assign.cc,v $
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* Revision 1.18 2004/08/28 15:08:31 steve
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* Do not change reg to wire in NetAssign_ unless synthesizing.
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*
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* Revision 1.17 2004/02/18 17:11:56 steve
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* Use perm_strings for named langiage items.
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*
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@ -292,37 +302,5 @@ NetAssignNB::~NetAssignNB()
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* Redo handling of assignment internal delays.
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* Leave it possible for them to be calculated
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* at run time.
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*
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* Revision 1.8 2001/08/25 23:50:03 steve
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* Change the NetAssign_ class to refer to the signal
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* instead of link into the netlist. This is faster
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* and uses less space. Make the NetAssignNB carry
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* the delays instead of the NetAssign_ lval objects.
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*
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* Change the vvp code generator to support multiple
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* l-values, i.e. concatenations of part selects.
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*
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* Revision 1.7 2001/07/25 03:10:49 steve
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* Create a config.h.in file to hold all the config
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* junk, and support gcc 3.0. (Stephan Boettcher)
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*
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* Revision 1.6 2000/10/18 20:04:39 steve
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* Add ivl_lval_t and support for assignment l-values.
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*
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* Revision 1.5 2000/09/20 02:53:15 steve
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* Correctly measure comples l-values of assignments.
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*
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* Revision 1.4 2000/09/10 02:18:16 steve
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* elaborate complex l-values
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*
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* Revision 1.3 2000/09/07 00:06:53 steve
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* encapsulate access to the l-value expected width.
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*
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* Revision 1.2 2000/09/02 23:40:13 steve
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* Pull NetAssign_ creation out of constructors.
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*
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* Revision 1.1 2000/09/02 20:54:20 steve
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* Rearrange NetAssign to make NetAssign_ separate.
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*
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*/
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11
netlist.h
11
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.h,v 1.315 2004/06/30 15:32:18 steve Exp $"
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#ident "$Id: netlist.h,v 1.316 2004/08/28 15:08:31 steve Exp $"
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#endif
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/*
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@ -1427,6 +1427,11 @@ class NetAssign_ {
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NetMemory*mem() const;
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NetVariable*var() const;
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// Mark that the synthesizer has worked with this l-value, so
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// when it is released, the l-value signal should be turned
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// into a wire.
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void turn_sig_to_wire_on_release();
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// This pointer is for keeping simple lists.
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NetAssign_* more;
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@ -1438,6 +1443,7 @@ class NetAssign_ {
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NetVariable*var_;
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NetExpr*bmux_;
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bool turn_sig_to_wire_on_release_;
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unsigned loff_;
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unsigned lwid_;
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};
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@ -3343,6 +3349,9 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.316 2004/08/28 15:08:31 steve
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* Do not change reg to wire in NetAssign_ unless synthesizing.
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*
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* Revision 1.315 2004/06/30 15:32:18 steve
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* nex_output for NetPDelay statements.
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*
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16
syn-rules.y
16
syn-rules.y
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: syn-rules.y,v 1.29 2004/02/20 18:53:35 steve Exp $"
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#ident "$Id: syn-rules.y,v 1.30 2004/08/28 15:08:32 steve Exp $"
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#endif
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# include "config.h"
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@ -131,6 +131,13 @@ static void hookup_DFF_CE(NetFF*ff, NetESignal*d, NetEvProbe*pclk,
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if (pclk->edge() == NetEvProbe::NEGEDGE)
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ff->attribute(perm_string::literal("Clock:LPM_Polarity"), verinum("INVERT"));
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/* This lval_ represents a reg that is a WIRE in the
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synthesized results. This function signals the destructor
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to change the REG that this l-value refers to into a
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WIRE. It is done then, at the last minute, so that pending
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synthesis can continue to work with it as a WIRE. */
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a->turn_sig_to_wire_on_release();
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}
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static void hookup_RAMDQ(NetRamDq*ram, NetESignal*d, NetNet*adr,
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@ -163,6 +170,13 @@ static void hookup_RAMDQ(NetRamDq*ram, NetESignal*d, NetNet*adr,
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same NetMemory, that have the same address pins and are
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otherwise compatible. This absorbs them into this object. */
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ram->absorb_partners();
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/* This lval_ represents a reg that is a WIRE in the
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synthesized results. This function signals the destructor
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to change the REG that this l-value refers to into a
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WIRE. It is done then, at the last minute, so that pending
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synthesis can continue to work with it as a WIRE. */
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a->turn_sig_to_wire_on_release();
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}
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static void make_DFF_CE(Design*des, NetProcTop*top, NetEvWait*wclk,
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12
synth2.cc
12
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.37 2004/03/15 18:40:12 steve Exp $"
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#ident "$Id: synth2.cc,v 1.38 2004/08/28 15:08:32 steve Exp $"
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#endif
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# include "config.h"
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@ -115,6 +115,13 @@ bool NetAssignBase::synth_async(Design*des, NetScope*scope,
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connect(nex_out->pin(ptr), rsig->pin(idx));
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}
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/* This lval_ represents a reg that is a WIRE in the
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synthesized results. This function signals the destructor
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to change the REG that this l-value refers to into a
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WIRE. It is done then, at the last minute, so that pending
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synthesis can continue to work with it as a WIRE. */
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lval_->turn_sig_to_wire_on_release();
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DEBUG_SYNTH2_EXIT("NetAssignBase",true)
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return true;
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}
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@ -978,6 +985,9 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.38 2004/08/28 15:08:32 steve
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* Do not change reg to wire in NetAssign_ unless synthesizing.
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*
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* Revision 1.37 2004/03/15 18:40:12 steve
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* Only include DEBUG_SYNTH2 if __FUNCTION__ defined.
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*
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