More xilinx common code.
This commit is contained in:
steve
parent
b810556d3f
commit
eb605694eb
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.29 2003/07/02 02:58:18 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.30 2003/07/02 03:02:15 steve Exp $"
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#endif
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# include "device.h"
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@ -53,66 +53,9 @@ const static struct edif_xlib_celltable virtex_celltable[] = {
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*/
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static void virtex_show_header(ivl_design_t des)
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{
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unsigned idx;
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ivl_scope_t root = ivl_design_root(des);
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unsigned sig_cnt = ivl_scope_sigs(root);
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unsigned nports = 0, pidx;
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const char*part_str = 0;
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/* Count the ports I'm going to use. */
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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nports += ivl_signal_pins(sig);
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}
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edf = edif_create(ivl_scope_basename(root), nports);
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pidx = 0;
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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edif_joint_t jnt;
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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if (ivl_signal_pins(sig) == 1) {
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edif_portconfig(edf, pidx, ivl_signal_basename(sig),
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ivl_signal_port(sig));
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assert(ivl_signal_pins(sig) == 1);
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
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edif_port_to_joint(jnt, edf, pidx);
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} else {
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const char*name = ivl_signal_basename(sig);
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ivl_signal_port_t dir = ivl_signal_port(sig);
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char buf[128];
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unsigned bit;
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for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
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const char*tmp;
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sprintf(buf, "%s[%u]", name, bit);
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tmp = strdup(buf);
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edif_portconfig(edf, pidx+bit, tmp, dir);
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jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
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edif_port_to_joint(jnt, edf, pidx+bit);
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}
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}
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pidx += ivl_signal_pins(sig);
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}
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assert(pidx == nports);
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xilinx_common_header(des);
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xlib = edif_xlibrary_create(edf, "VIRTEX");
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edif_xlibrary_set_celltable(xlib, virtex_celltable);
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@ -130,39 +73,6 @@ static void virtex_show_header(ivl_design_t des)
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}
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void virtex_show_footer(ivl_design_t des)
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{
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unsigned idx;
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for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
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unsigned pin;
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ivl_net_const_t net = ivl_design_const(des, idx);
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const char*val = ivl_const_bits(net);
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for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
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edif_joint_t jnt;
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edif_cellref_t pad;
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jnt = edif_joint_of_nexus(edf, ivl_const_pin(net, pin));
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switch (val[pin]) {
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case '0':
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pad = edif_cellref_create(edf, cell_0);
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break;
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case '1':
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pad = edif_cellref_create(edf, cell_1);
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break;
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default:
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assert(0);
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break;
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}
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edif_add_to_joint(jnt, pad, 0);
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}
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}
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edif_print(xnf, edf);
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}
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static void virtex_or_wide(ivl_net_logic_t net)
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{
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edif_cell_t cell_muxcy_l = xilinx_cell_muxcy_l(xlib);
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@ -832,7 +742,7 @@ void virtex_add(ivl_lpm_t net)
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const struct device_s d_virtex_edif = {
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virtex_show_header,
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virtex_show_footer,
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xilinx_show_footer,
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xilinx_show_scope,
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xilinx_pad,
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virtex_logic,
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@ -850,6 +760,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.30 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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* Revision 1.29 2003/07/02 02:58:18 steve
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* Remember to set INIT on wide-or trailing luts.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.16 2003/06/28 04:18:47 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.17 2003/07/02 03:02:15 steve Exp $"
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#endif
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# include "device.h"
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@ -54,66 +54,9 @@ const static struct edif_xlib_celltable virtex2_celltable[] = {
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*/
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static void virtex2_show_header(ivl_design_t des)
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{
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unsigned idx;
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ivl_scope_t root = ivl_design_root(des);
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unsigned sig_cnt = ivl_scope_sigs(root);
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unsigned nports = 0, pidx;
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const char*part_str = 0;
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/* Count the ports I'm going to use. */
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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nports += ivl_signal_pins(sig);
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}
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edf = edif_create(ivl_scope_basename(root), nports);
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pidx = 0;
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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edif_joint_t jnt;
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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if (ivl_signal_pins(sig) == 1) {
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edif_portconfig(edf, pidx, ivl_signal_basename(sig),
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ivl_signal_port(sig));
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assert(ivl_signal_pins(sig) == 1);
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
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edif_port_to_joint(jnt, edf, pidx);
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} else {
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const char*name = ivl_signal_basename(sig);
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ivl_signal_port_t dir = ivl_signal_port(sig);
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char buf[128];
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unsigned bit;
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for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
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const char*tmp;
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sprintf(buf, "%s[%u]", name, bit);
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tmp = strdup(buf);
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edif_portconfig(edf, pidx+bit, tmp, dir);
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jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
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edif_port_to_joint(jnt, edf, pidx+bit);
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}
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}
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pidx += ivl_signal_pins(sig);
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}
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assert(pidx == nports);
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xilinx_common_header(des);
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xlib = edif_xlibrary_create(edf, "VIRTEX2");
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edif_xlibrary_set_celltable(xlib, virtex2_celltable);
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@ -133,7 +76,7 @@ static void virtex2_show_header(ivl_design_t des)
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const struct device_s d_virtex2_edif = {
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virtex2_show_header,
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virtex_show_footer,
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xilinx_show_footer,
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xilinx_show_scope,
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xilinx_pad,
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virtex_logic,
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@ -151,6 +94,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.17 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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* Revision 1.16 2003/06/28 04:18:47 steve
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* Add support for wide OR/NOR gates.
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*
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@ -17,12 +17,13 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.c,v 1.5 2003/07/02 00:25:40 steve Exp $"
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#ident "$Id: xilinx.c,v 1.6 2003/07/02 03:02:15 steve Exp $"
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#endif
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# include "edif.h"
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# include "generic.h"
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# include "xilinx.h"
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# include "fpga_priv.h"
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# include <stdlib.h>
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# include <string.h>
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#ifdef HAVE_MALLOC_H
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@ -230,6 +231,107 @@ edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib)
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return cell;
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}
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/*
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* This function does a lot of the stuff common to the header
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* functions of various Xilinx familes. This includes creating the edf
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* object that holds the netlist.
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*/
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void xilinx_common_header(ivl_design_t des)
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{
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unsigned idx;
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ivl_scope_t root = ivl_design_root(des);
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unsigned sig_cnt = ivl_scope_sigs(root);
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unsigned nports = 0, pidx;
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/* Count the ports I'm going to use. */
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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nports += ivl_signal_pins(sig);
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}
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edf = edif_create(ivl_scope_basename(root), nports);
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pidx = 0;
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for (idx = 0 ; idx < sig_cnt ; idx += 1) {
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edif_joint_t jnt;
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ivl_signal_t sig = ivl_scope_sig(root, idx);
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if (ivl_signal_port(sig) == IVL_SIP_NONE)
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continue;
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if (ivl_signal_attr(sig, "PAD") != 0)
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continue;
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if (ivl_signal_pins(sig) == 1) {
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edif_portconfig(edf, pidx, ivl_signal_basename(sig),
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ivl_signal_port(sig));
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assert(ivl_signal_pins(sig) == 1);
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jnt = edif_joint_of_nexus(edf, ivl_signal_pin(sig, 0));
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edif_port_to_joint(jnt, edf, pidx);
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} else {
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const char*name = ivl_signal_basename(sig);
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ivl_signal_port_t dir = ivl_signal_port(sig);
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char buf[128];
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unsigned bit;
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for (bit = 0 ; bit < ivl_signal_pins(sig) ; bit += 1) {
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const char*tmp;
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sprintf(buf, "%s[%u]", name, bit);
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tmp = strdup(buf);
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edif_portconfig(edf, pidx+bit, tmp, dir);
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jnt = edif_joint_of_nexus(edf,ivl_signal_pin(sig,bit));
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edif_port_to_joint(jnt, edf, pidx+bit);
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}
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}
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pidx += ivl_signal_pins(sig);
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}
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assert(pidx == nports);
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}
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void xilinx_show_footer(ivl_design_t des)
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{
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unsigned idx;
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for (idx = 0 ; idx < ivl_design_consts(des) ; idx += 1) {
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unsigned pin;
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ivl_net_const_t net = ivl_design_const(des, idx);
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const char*val = ivl_const_bits(net);
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for (pin = 0 ; pin < ivl_const_pins(net) ; pin += 1) {
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edif_joint_t jnt;
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edif_cellref_t pad;
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jnt = edif_joint_of_nexus(edf, ivl_const_pin(net, pin));
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switch (val[pin]) {
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case '0':
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pad = edif_cellref_create(edf, cell_0);
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break;
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case '1':
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pad = edif_cellref_create(edf, cell_1);
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break;
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default:
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assert(0);
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break;
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}
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edif_add_to_joint(jnt, pad, 0);
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}
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}
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edif_print(xnf, edf);
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}
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/*
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* Make (or retrieve) a cell in the external library that reflects the
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* scope with its ports.
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@ -792,6 +894,9 @@ void xilinx_shiftl(ivl_lpm_t net)
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/*
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* $Log: xilinx.c,v $
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* Revision 1.6 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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* Revision 1.5 2003/07/02 00:25:40 steve
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* Add xilinx support for bufif1.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.h,v 1.5 2003/07/02 00:25:40 steve Exp $"
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#ident "$Id: xilinx.h,v 1.6 2003/07/02 03:02:15 steve Exp $"
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#endif
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/*
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@ -98,13 +98,14 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
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/* === Inheritable Methods === */
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extern void virtex_show_footer(ivl_design_t des);
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extern void virtex_logic(ivl_net_logic_t net);
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extern void virtex_generic_dff(ivl_lpm_t net);
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extern void virtex_eq(ivl_lpm_t net);
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extern void virtex_ge(ivl_lpm_t net);
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extern void virtex_add(ivl_lpm_t net);
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extern void xilinx_common_header(ivl_design_t des);
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extern void xilinx_show_footer(ivl_design_t des);
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extern void xilinx_show_scope(ivl_scope_t scope);
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extern void xilinx_pad(ivl_signal_t, const char*str);
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extern void xilinx_logic(ivl_net_logic_t net);
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@ -114,6 +115,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
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/*
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* $Log: xilinx.h,v $
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* Revision 1.6 2003/07/02 03:02:15 steve
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* More xilinx common code.
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*
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* Revision 1.5 2003/07/02 00:25:40 steve
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* Add xilinx support for bufif1.
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*
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