Virtex support for mux devices and adders
with carry chains. Also, make Virtex specific implementations of primitive logic.
This commit is contained in:
steve
parent
0253f92e7e
commit
4507351d48
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: d-generic-edif.c,v 1.3 2001/09/06 04:28:40 steve Exp $"
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#ident "$Id: d-generic-edif.c,v 1.4 2001/09/09 22:23:28 steve Exp $"
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# include "device.h"
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# include "fpga_priv.h"
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@ -347,30 +347,33 @@ void edif_show_generic_dff(ivl_lpm_t net)
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{
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ivl_nexus_t nex;
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char jbuf[1024];
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unsigned idx;
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assert(ivl_lpm_width(net) == 1);
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for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
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edif_uref += 1;
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edif_uref += 1;
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fprintf(xnf, "(instance (rename U%u \"%s\")", edif_uref, ivl_lpm_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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fprintf(xnf, "(instance (rename U%u \"%s[%u]\")",
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edif_uref, ivl_lpm_name(net), idx);
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef FDCE (libraryRef VIRTEX))))\n");
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nex = ivl_lpm_q(net, 0);
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sprintf(jbuf, "(portRef Q (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_data(net, 0);
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sprintf(jbuf, "(portRef D (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_clk(net);
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sprintf(jbuf, "(portRef C (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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if ((nex = ivl_lpm_enable(net))) {
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sprintf(jbuf, "(portRef CE (instanceRef U%u))", edif_uref);
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nex = ivl_lpm_q(net, idx);
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sprintf(jbuf, "(portRef Q (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_data(net, idx);
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sprintf(jbuf, "(portRef D (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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nex = ivl_lpm_clk(net);
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sprintf(jbuf, "(portRef C (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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if ((nex = ivl_lpm_enable(net))) {
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sprintf(jbuf, "(portRef CE (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(nex, jbuf);
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}
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}
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}
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@ -389,6 +392,11 @@ const struct device_s d_generic_edif = {
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/*
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* $Log: d-generic-edif.c,v $
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* Revision 1.4 2001/09/09 22:23:28 steve
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* Virtex support for mux devices and adders
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* with carry chains. Also, make Virtex specific
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* implementations of primitive logic.
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*
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* Revision 1.3 2001/09/06 04:28:40 steve
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* Separate the virtex and generic-edif code generators.
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*
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@ -16,7 +16,7 @@
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ident "$Id: d-virtex.c,v 1.1 2001/09/06 04:28:40 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.2 2001/09/09 22:23:28 steve Exp $"
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# include "device.h"
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# include "fpga_priv.h"
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@ -27,18 +27,34 @@
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/*
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* This is the EDIF code generator for VIRTEX style parts. It uses the
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* VIRTEX primitives from the unified library.
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* following VIRTEX primitives from the unified library.
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*
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* BUF O, I
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* non-inverting buffer. This device is typically removed by the
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* place-and-route step, as it is not normally needed within an
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* FPGA net.
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*
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* INV O, I
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* Inverting buffer.
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*
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* LUT2 O, I0, I1
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* LUT3 O, I0, I1, I2
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* LUT4 O, I0, I1, I2, I3
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* These are look-up tables. They represent the LUT sub-devices
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* that live in the CLBs, 2 per slice. The logic value of the
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* device itself is given by an INIT property.
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*
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* The INIT property is a string of hex digits. The binary value
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* that the digits represents is the outputs addressed by the
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* inputs. For example, to get an AND2 from LUT2, INIT=8.
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*
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* MUXCY_L LO, S, DI, CI
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*
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* XORCY O, LI, CI
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*/
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static const char*virtex_library_text =
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" (external VIRTEX (edifLevel 0) (technology (numberDefinition))\n"
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" (cell AND2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell BUF (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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@ -57,14 +73,20 @@ static const char*virtex_library_text =
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port G (direction OUTPUT)))))\n"
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" (cell NOR2 (cellType GENERIC)\n"
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" (cell INV (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I (direction INPUT)))))\n"
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" (cell LUT2 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT)))))\n"
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" (cell NOR3 (cellType GENERIC)\n"
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" (cell LUT3 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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@ -72,10 +94,34 @@ static const char*virtex_library_text =
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT))\n"
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" (port I2 (direction INPUT)))))\n"
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" (cell LUT4 (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port I0 (direction INPUT))\n"
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" (port I1 (direction INPUT))\n"
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" (port I2 (direction INPUT))\n"
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" (port I3 (direction INPUT)))))\n"
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" (cell MUXCY_L (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port LO (direction OUTPUT))\n"
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" (port S (direction INPUT))\n"
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" (port DI (direction INPUT))\n"
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" (port CI (direction INPUT)))))\n"
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" (cell VCC (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface (port P (direction OUTPUT)))))\n"
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" (cell XORCY (cellType GENERIC)\n"
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" (view Netlist_representation\n"
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" (viewType NETLIST)\n"
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" (interface\n"
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" (port O (direction OUTPUT))\n"
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" (port LI (direction INPUT))\n"
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" (port CI (direction INPUT)))))\n"
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" )\n"
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;
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@ -85,32 +131,120 @@ static void edif_show_header(ivl_design_t des)
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edif_show_header_generic(des, virtex_library_text);
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}
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static void edif_show_logic(ivl_net_logic_t net)
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static void edif_show_lut2(const char*name, unsigned uref,
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ivl_nexus_t O, ivl_nexus_t I0, ivl_nexus_t I1,
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const char*truth_table)
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{
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char jbuf[1024];
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fprintf(xnf, "(instance (rename U%u \"%s\")"
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" (property INIT (string \"%s\"))",
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uref, name, truth_table);
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef LUT2 (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(O, jbuf);
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sprintf(jbuf, "(portRef I0 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I0, jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I1, jbuf);
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}
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static void edif_show_lut3(const char*name, unsigned uref,
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ivl_nexus_t O,
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ivl_nexus_t I0,
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ivl_nexus_t I1,
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ivl_nexus_t I2,
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const char*truth_table)
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{
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char jbuf[1024];
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fprintf(xnf, "(instance (rename U%u \"%s\")"
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" (property INIT (string \"%s\"))",
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uref, name, truth_table);
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef LUT3 (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(O, jbuf);
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sprintf(jbuf, "(portRef I0 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I0, jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I1, jbuf);
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sprintf(jbuf, "(portRef I2 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I2, jbuf);
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}
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static void edif_show_lut4(const char*name, unsigned uref,
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ivl_nexus_t O,
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ivl_nexus_t I0, ivl_nexus_t I1,
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ivl_nexus_t I2, ivl_nexus_t I3,
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const char*truth_table)
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{
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char jbuf[1024];
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fprintf(xnf, "(instance (rename U%u \"%s\")"
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" (property INIT (string \"%s\"))",
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uref, name, truth_table);
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef LUT4 (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(O, jbuf);
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sprintf(jbuf, "(portRef I0 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I0, jbuf);
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sprintf(jbuf, "(portRef I1 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I1, jbuf);
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sprintf(jbuf, "(portRef I2 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I2, jbuf);
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sprintf(jbuf, "(portRef I3 (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(I3, jbuf);
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}
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static void edif_show_virtex_logic(ivl_net_logic_t net)
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{
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char jbuf[1024];
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unsigned idx;
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edif_uref += 1;
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switch (ivl_logic_type(net)) {
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case IVL_LO_AND:
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assert(ivl_logic_pins(net) <= 10);
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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edif_uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef AND%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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switch (ivl_logic_pins(net)) {
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case 3:
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edif_show_lut2(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2), "8");
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break;
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case 4:
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edif_show_lut3(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3), "80");
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break;
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case 5:
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edif_show_lut4(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3),
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ivl_logic_pin(net, 4), "8000");
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break;
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}
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break;
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@ -129,45 +263,292 @@ static void edif_show_logic(ivl_net_logic_t net)
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break;
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case IVL_LO_NOR:
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assert(ivl_logic_pins(net) <= 10);
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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case 3:
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edif_show_lut2(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2), "1");
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break;
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case 4:
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edif_show_lut3(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3), "01");
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break;
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case 5:
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edif_show_lut4(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3),
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ivl_logic_pin(net, 4), "0001");
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break;
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}
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break;
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case IVL_LO_NOT:
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assert(ivl_logic_pins(net) == 2);
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fprintf(xnf, "(instance (rename U%u \"%s\")",
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edif_uref, ivl_logic_name(net));
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fprintf(xnf, " (viewRef Netlist_representation"
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" (cellRef NOR%u (libraryRef VIRTEX))))\n",
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ivl_logic_pins(net) - 1);
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" (cellRef INV (libraryRef VIRTEX))))\n");
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sprintf(jbuf, "(portRef O (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 0), jbuf);
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for (idx = 1 ; idx < ivl_logic_pins(net) ; idx += 1) {
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sprintf(jbuf, "(portRef I%u (instanceRef U%u))",
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idx-1, edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, idx), jbuf);
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sprintf(jbuf, "(portRef I (instanceRef U%u))", edif_uref);
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edif_set_nexus_joint(ivl_logic_pin(net, 1), jbuf);
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break;
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case IVL_LO_OR:
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assert(ivl_logic_pins(net) <= 5);
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assert(ivl_logic_pins(net) >= 3);
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switch (ivl_logic_pins(net)) {
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case 3:
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edif_show_lut2(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2), "E");
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break;
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case 4:
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edif_show_lut3(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3), "FE");
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break;
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case 5:
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edif_show_lut4(ivl_logic_name(net), edif_uref,
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ivl_logic_pin(net, 0),
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ivl_logic_pin(net, 1),
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ivl_logic_pin(net, 2),
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ivl_logic_pin(net, 3),
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ivl_logic_pin(net, 4), "FFFE");
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break;
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}
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break;
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default:
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fprintf(stderr, "UNSUPPORT LOGIC TYPE: %u\n", ivl_logic_type(net));
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fprintf(stderr, "UNSUPPORTED LOGIC TYPE: %u\n",
|
||||
ivl_logic_type(net));
|
||||
}
|
||||
}
|
||||
|
||||
static void edif_show_virtex_eq(ivl_lpm_t net)
|
||||
{
|
||||
assert(ivl_lpm_width(net) >= 1);
|
||||
|
||||
edif_uref += 1;
|
||||
|
||||
switch (ivl_lpm_width(net)) {
|
||||
case 1:
|
||||
edif_show_lut2(ivl_lpm_name(net), edif_uref,
|
||||
ivl_lpm_q(net, 0),
|
||||
ivl_lpm_data(net, 0),
|
||||
ivl_lpm_datab(net, 0), "9");
|
||||
break;
|
||||
|
||||
case 2:
|
||||
edif_show_lut4(ivl_lpm_name(net), edif_uref,
|
||||
ivl_lpm_q(net, 0),
|
||||
ivl_lpm_data(net, 0), ivl_lpm_datab(net, 0),
|
||||
ivl_lpm_data(net, 1), ivl_lpm_datab(net, 1),
|
||||
"9009");
|
||||
break;
|
||||
|
||||
default:
|
||||
fprintf(stderr, "internal error: IVL_LPM_CMP_EQ: "
|
||||
"Unsupported width (%u)\n", ivl_lpm_width(net));
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This supports the general MUX with a single select input. The
|
||||
* output is selected from one of two inputs.
|
||||
*
|
||||
* This implements the mux a bit slice at a time. Each slice is a
|
||||
* 1-bit mux implemented with a three input LUT: I0 and I1 are the
|
||||
* alternative inputs, and I2 is the select.
|
||||
*
|
||||
* FIXME: In the long run, it would be cool to detect that the inputs
|
||||
* of the mux are themselves LUT devices and generate MUXF5 devices in
|
||||
* those cases. This currently does *not* do that.
|
||||
*/
|
||||
static void edif_show_virtex_mux(ivl_lpm_t net)
|
||||
{
|
||||
unsigned idx;
|
||||
assert(ivl_lpm_width(net) >= 1);
|
||||
assert(ivl_lpm_selects(net) == 1);
|
||||
|
||||
for (idx = 0 ; idx < ivl_lpm_width(net) ; idx += 1) {
|
||||
char tmp_name[1024];
|
||||
|
||||
edif_uref += 1;
|
||||
sprintf(tmp_name, "%s<%u>", ivl_lpm_name(net), idx);
|
||||
|
||||
edif_show_lut3(tmp_name, edif_uref,
|
||||
ivl_lpm_q(net, idx),
|
||||
ivl_lpm_data2(net, 0, idx),
|
||||
ivl_lpm_data2(net, 1, idx),
|
||||
ivl_lpm_select(net, 0),
|
||||
"CA");
|
||||
}
|
||||
}
|
||||
|
||||
static void edif_show_virtex_add(ivl_lpm_t net)
|
||||
{
|
||||
char jbuf [1024];
|
||||
unsigned idx;
|
||||
unsigned nref = 0;
|
||||
|
||||
/* Handle the special case that the adder is only one bit
|
||||
wide. Generate an XOR gate to perform the half-add. */
|
||||
if (ivl_lpm_width(net) == 1) {
|
||||
edif_uref += 1;
|
||||
|
||||
edif_show_lut2(ivl_lpm_name(net), edif_uref,
|
||||
ivl_lpm_q(net, 0),
|
||||
ivl_lpm_data(net, 0),
|
||||
ivl_lpm_datab(net, 0),
|
||||
"6");
|
||||
return;
|
||||
}
|
||||
|
||||
assert(ivl_lpm_width(net) > 1);
|
||||
edif_uref += 1;
|
||||
|
||||
/* First, draw the bottom bit slice of the adder. This
|
||||
includes the LUT2 device to perform the addition, and a
|
||||
MUXCY_L device to send the carry up to the next bit. */
|
||||
fprintf(xnf, "(instance (rename U%u_L0 \"%s\"[0])"
|
||||
" (property INIT (string \"6\"))", edif_uref,
|
||||
ivl_lpm_name(net));
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef LUT2 (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(instance U%u_M0", edif_uref);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef MUXCY_L (libraryRef VIRTEX))))\n");
|
||||
|
||||
sprintf(jbuf, "(portRef I0 (instanceRef U%u_L0))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_lpm_data(net, 0), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef I1 (instanceRef U%u_L0))", edif_uref);
|
||||
edif_set_nexus_joint(ivl_lpm_datab(net, 0), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u_L0))"
|
||||
" (portRef S (instanceRef U%u_M0))",
|
||||
edif_uref, edif_uref);
|
||||
edif_set_nexus_joint(ivl_lpm_q(net, 0), jbuf);
|
||||
|
||||
/* Now draw all the inside bit slices. These include the LUT2
|
||||
device for the basic add, the MUXCY_L device to propagate
|
||||
the carry, and an XORCY device to generate the real
|
||||
output. The XORCY device carries the name of the LPM
|
||||
device, the other devices have local names. */
|
||||
for (idx = 1 ; idx < (ivl_lpm_width(net)-1) ; idx += 1) {
|
||||
|
||||
fprintf(xnf, "(instance U%u_L%u) (property INIT (string \"6\"))",
|
||||
edif_uref, idx);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef LUT2 (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(instance U%u_M%u", edif_uref, idx);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef MUXCY_L (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(instance (rename U%u_X%u \"%s[%u]\")",
|
||||
edif_uref, idx, ivl_lpm_name(net), idx);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef XORCY (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(net U%uN%u (joined"
|
||||
" (portRef O (instanceRef U%u_L%u))"
|
||||
" (portRef S (instanceRef U%u_M%u))"
|
||||
" (portRef LI (instanceRef U%u_X%u))))\n",
|
||||
edif_uref, nref++, edif_uref, idx, edif_uref, idx,
|
||||
edif_uref, idx);
|
||||
|
||||
fprintf(xnf, "(net U%uN%u (joined"
|
||||
" (portRef CI (instanceRef U%u_M%u))"
|
||||
" (portRef CI (instanceRef U%u_X%u))"
|
||||
" (portRef LO (instanceRef U%u_M%u))))\n",
|
||||
edif_uref, nref++, edif_uref, idx, edif_uref, idx,
|
||||
edif_uref, idx-1);
|
||||
|
||||
sprintf(jbuf, "(portRef I0 (instanceRef U%u_L%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_data(net, idx), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef I1 (instanceRef U%u_L%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_datab(net, idx), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u_X%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_q(net, idx), jbuf);
|
||||
}
|
||||
|
||||
|
||||
fprintf(xnf, "(instance U%u_L%u) (property INIT (string \"6\"))",
|
||||
edif_uref, idx);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef LUT2 (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(instance (rename U%u_X%u \"%s[%u]\")",
|
||||
edif_uref, idx, ivl_lpm_name(net), idx);
|
||||
fprintf(xnf, " (viewRef Netlist_representation"
|
||||
" (cellRef XORCY (libraryRef VIRTEX))))\n");
|
||||
|
||||
fprintf(xnf, "(net U%uN%u (joined"
|
||||
" (portRef O (instanceRef U%u_L%u))"
|
||||
" (portRef LI (instanceRef U%u_X%u))))\n",
|
||||
edif_uref, nref++, edif_uref, idx, edif_uref, idx);
|
||||
|
||||
fprintf(xnf, "(net U%uN%u (joined"
|
||||
" (portRef CI (instanceRef U%u_X%u))"
|
||||
" (portRef LO (instanceRef U%u_M%u))))\n",
|
||||
edif_uref, nref++, edif_uref, idx, edif_uref, idx-1);
|
||||
|
||||
sprintf(jbuf, "(portRef I0 (instanceRef U%u_L%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_data(net, idx), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef I1 (instanceRef U%u_L%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_datab(net, idx), jbuf);
|
||||
|
||||
sprintf(jbuf, "(portRef O (instanceRef U%u_X%u))",
|
||||
edif_uref, idx);
|
||||
edif_set_nexus_joint(ivl_lpm_q(net, idx), jbuf);
|
||||
}
|
||||
|
||||
const struct device_s d_virtex_edif = {
|
||||
edif_show_header,
|
||||
edif_show_footer,
|
||||
edif_show_logic,
|
||||
edif_show_virtex_logic,
|
||||
edif_show_generic_dff,
|
||||
edif_show_virtex_eq,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0
|
||||
edif_show_virtex_mux,
|
||||
edif_show_virtex_add
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* $Log: d-virtex.c,v $
|
||||
* Revision 1.2 2001/09/09 22:23:28 steve
|
||||
* Virtex support for mux devices and adders
|
||||
* with carry chains. Also, make Virtex specific
|
||||
* implementations of primitive logic.
|
||||
*
|
||||
* Revision 1.1 2001/09/06 04:28:40 steve
|
||||
* Separate the virtex and generic-edif code generators.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ident "$Id: gates.c,v 1.6 2001/09/02 21:33:07 steve Exp $"
|
||||
#ident "$Id: gates.c,v 1.7 2001/09/09 22:23:28 steve Exp $"
|
||||
|
||||
# include <ivl_target.h>
|
||||
# include "fpga_priv.h"
|
||||
|
|
@ -32,22 +32,47 @@ static void show_gate_lpm(ivl_lpm_t net)
|
|||
switch (ivl_lpm_type(net)) {
|
||||
|
||||
case IVL_LPM_ADD:
|
||||
if (device->show_add == 0) {
|
||||
fprintf(stderr, "fpga.tgt: IVL_LPM_ADD not supported"
|
||||
" by this target.\n");
|
||||
return;
|
||||
}
|
||||
device->show_add(net);
|
||||
break;
|
||||
|
||||
case IVL_LPM_CMP_EQ:
|
||||
if (device->show_cmp_eq == 0) {
|
||||
fprintf(stderr, "fpga.tgt: IVL_LPM_CMP_EQ not supported"
|
||||
" by this target.\n");
|
||||
return;
|
||||
}
|
||||
device->show_cmp_eq(net);
|
||||
break;
|
||||
|
||||
case IVL_LPM_CMP_NE:
|
||||
if (device->show_cmp_ne == 0) {
|
||||
fprintf(stderr, "fpga.tgt: IVL_LPM_CMP_NE not supported"
|
||||
" by this target.\n");
|
||||
return;
|
||||
}
|
||||
device->show_cmp_ne(net);
|
||||
break;
|
||||
|
||||
case IVL_LPM_FF:
|
||||
if (device->show_dff == 0) {
|
||||
fprintf(stderr, "fpga.tgt: IVL_LPM_FF not supported"
|
||||
" by this target.\n");
|
||||
return;
|
||||
}
|
||||
device->show_dff(net);
|
||||
break;
|
||||
|
||||
case IVL_LPM_MUX:
|
||||
if (device->show_mux == 0) {
|
||||
fprintf(stderr, "fpga.tgt: IVL_LPM_MUX not supported"
|
||||
" by this target.\n");
|
||||
return;
|
||||
}
|
||||
device->show_mux(net);
|
||||
break;
|
||||
|
||||
|
|
@ -73,6 +98,11 @@ int show_scope_gates(ivl_scope_t net, void*x)
|
|||
|
||||
/*
|
||||
* $Log: gates.c,v $
|
||||
* Revision 1.7 2001/09/09 22:23:28 steve
|
||||
* Virtex support for mux devices and adders
|
||||
* with carry chains. Also, make Virtex specific
|
||||
* implementations of primitive logic.
|
||||
*
|
||||
* Revision 1.6 2001/09/02 21:33:07 steve
|
||||
* Rearrange the XNF code generator to be generic-xnf
|
||||
* so that non-XNF code generation is also possible.
|
||||
|
|
|
|||
Loading…
Reference in New Issue