Fix synth2 handling of aset/aclr signals where
flip-flops are split by begin-end blocks.
This commit is contained in:
steve
parent
3d4593d4d5
commit
9ce2806710
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: design_dump.cc,v 1.134 2002/10/19 22:59:49 steve Exp $"
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#ident "$Id: design_dump.cc,v 1.135 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "config.h"
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@ -271,7 +271,8 @@ void NetConst::dump_node(ostream&o, unsigned ind) const
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void NetFF::dump_node(ostream&o, unsigned ind) const
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{
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o << setw(ind) << "" << "LPM_FF: " << name()
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<< " scope=" << (scope()? scope()->name() : "") << endl;
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<< " scope=" << (scope()? scope()->name() : "")
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<< " aset_value=" << aset_value_ << endl;
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dump_node_pins(o, ind+4);
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dump_obj_attr(o, ind+4);
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@ -1003,6 +1004,10 @@ void Design::dump(ostream&o) const
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/*
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* $Log: design_dump.cc,v $
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* Revision 1.135 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.134 2002/10/19 22:59:49 steve
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* Redo the parameter vector support to allow
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* parameter names in range expressions.
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1
ivl.def
1
ivl.def
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@ -54,6 +54,7 @@ ivl_logic_pin
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ivl_logic_pins
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ivl_logic_udp
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ivl_lpm_aset_value
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ivl_lpm_async_clr
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ivl_lpm_async_set
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ivl_lpm_basename
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: ivl_target.h,v 1.107 2002/09/26 03:18:04 steve Exp $"
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#ident "$Id: ivl_target.h,v 1.108 2002/10/23 01:47:17 steve Exp $"
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#endif
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#ifdef __cplusplus
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@ -615,6 +615,7 @@ extern unsigned ivl_lpm_width(ivl_lpm_t net);
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/* IVL_LPM_FF */
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extern ivl_nexus_t ivl_lpm_async_clr(ivl_lpm_t net);
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extern ivl_nexus_t ivl_lpm_async_set(ivl_lpm_t net);
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extern ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net);
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/* IVL_LPM_FF IVL_LPM_RAM */
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extern ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net);
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/* IVL_LPM_UFUNC */
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@ -1090,6 +1091,10 @@ _END_DECL
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/*
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* $Log: ivl_target.h,v $
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* Revision 1.108 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.107 2002/09/26 03:18:04 steve
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* Generate vvp code for asynch set/reset of NetFF.
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*
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16
netlist.cc
16
netlist.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.cc,v 1.200 2002/09/26 03:18:04 steve Exp $"
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#ident "$Id: netlist.cc,v 1.201 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "config.h"
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@ -650,6 +650,16 @@ const Link& NetFF::pin_Q(unsigned w) const
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return pin(pn);
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}
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void NetFF::aset_value(const verinum&val)
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{
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aset_value_ = val;
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}
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const verinum& NetFF::aset_value() const
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{
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return aset_value_;
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}
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/*
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* The NetAddSub class represents an LPM_ADD_SUB device. The pinout is
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@ -2310,6 +2320,10 @@ const NetProc*NetTaskDef::proc() const
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/*
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* $Log: netlist.cc,v $
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* Revision 1.201 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.200 2002/09/26 03:18:04 steve
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* Generate vvp code for asynch set/reset of NetFF.
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*
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12
netlist.h
12
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: netlist.h,v 1.266 2002/10/21 01:42:08 steve Exp $"
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#ident "$Id: netlist.h,v 1.267 2002/10/23 01:47:17 steve Exp $"
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#endif
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/*
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@ -671,9 +671,15 @@ class NetFF : public NetNode {
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const Link& pin_Data(unsigned) const;
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const Link& pin_Q(unsigned) const;
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void aset_value(const verinum&val);
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const verinum& aset_value() const;
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virtual void dump_node(ostream&, unsigned ind) const;
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virtual bool emit_node(struct target_t*) const;
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virtual void functor_node(Design*des, functor_t*fun);
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private:
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verinum aset_value_;
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};
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@ -3077,6 +3083,10 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.267 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.266 2002/10/21 01:42:08 steve
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* Synthesizer support for synchronous begin-end blocks.
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*
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62
synth2.cc
62
synth2.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: synth2.cc,v 1.16 2002/10/21 01:42:09 steve Exp $"
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#ident "$Id: synth2.cc,v 1.17 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "config.h"
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@ -333,16 +333,24 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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NetNet*tmp_out = new NetNet(scope, "tmp2", NetNet::WIRE,
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tmp_set.count());
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verinum tmp_aset = ff->aset_value();
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/* Create a new DFF to handle this part of the begin-end
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block. Connect this NetFF to the associated pins of
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the existing wide NetFF device. */
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the existing wide NetFF device. While I'm at it, also
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copy the aset_value bits for the new ff device. */
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NetFF*ff2 = new NetFF(scope, scope->local_hsymbol().c_str(),
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tmp_out->pin_count());
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des->add_node(ff2);
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verinum aset_value2 (verinum::V1, ff2->width());
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for (unsigned idx = 0 ; idx < ff2->width() ; idx += 1) {
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connect(ff->pin_Data(idx+offset), ff2->pin_Data(idx));
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connect(ff->pin_Q(idx+offset), ff2->pin_Q(idx));
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unsigned ptr = find_nexus_in_set(nex_map, tmp_set[idx]);
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connect(ff->pin_Data(ptr), ff2->pin_Data(idx));
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connect(ff->pin_Q(ptr), ff2->pin_Q(idx));
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if (ptr < tmp_aset.len())
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aset_value2.set(idx, tmp_aset[ptr]);
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}
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if (ff->pin_Aclr().is_linked())
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connect(ff->pin_Aclr(), ff2->pin_Aclr());
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@ -353,6 +361,23 @@ bool NetBlock::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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if (ff->pin_Enable().is_linked())
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connect(ff->pin_Enable(),ff2->pin_Enable());
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/* Remember to store the aset value into the new FF. If
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this leads to an Aset value of 0 (and Aclr is not
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otherwise used) then move the Aset input to Aclr. */
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if (tmp_aset.len() == ff->width()) {
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if ((aset_value2.as_ulong() == 0)
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&& ff2->pin_Aset().is_linked()
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&& !ff2->pin_Aclr().is_linked()) {
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connect(ff2->pin_Aclr(), ff2->pin_Aset());
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ff2->pin_Aset().unlink();
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} else {
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ff2->aset_value(aset_value2);
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}
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}
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/* Now go on with the synchronous synthesis for this
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subset of the statement. */
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bool ok_flag = cur->synth_sync(des, scope, ff2, tmp_map,
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@ -415,16 +440,25 @@ bool NetCondit::synth_sync(Design*des, NetScope*scope, NetFF*ff,
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if_->synth_async(des, scope, nex_map, asig);
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assert(asig->pin_count() == ff->width());
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assert(asig->pin(0).nexus()->drivers_constant());
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switch (asig->pin(0).nexus()->driven_value()) {
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case verinum::V0:
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/* Collect the set/reset value into a verinum. If
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this turns out to be entirely 0 values, then
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use the Aclr input. Otherwise, use the Aset
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input and save the set value. */
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verinum tmp (verinum::V0, ff->width());
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for (unsigned bit = 0 ; bit < ff->width() ; bit += 1) {
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assert(asig->pin(bit).nexus()->drivers_constant());
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tmp.set(bit, asig->pin(bit).nexus()->driven_value());
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}
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assert(tmp.is_defined());
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if (tmp.as_ulong() == 0) {
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connect(ff->pin_Aclr(), ce->pin(0));
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break;
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case verinum::V1:
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} else {
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connect(ff->pin_Aset(), ce->pin(0));
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break;
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default:
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assert(0);
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ff->aset_value(tmp);
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}
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delete asig;
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@ -655,6 +689,10 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.17 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.16 2002/10/21 01:42:09 steve
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* Synthesizer support for synchronous begin-end blocks.
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*
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18
t-dll-api.cc
18
t-dll-api.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll-api.cc,v 1.87 2002/09/26 03:18:04 steve Exp $"
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#ident "$Id: t-dll-api.cc,v 1.88 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "config.h"
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@ -577,6 +577,18 @@ extern "C" ivl_nexus_t ivl_lpm_clk(ivl_lpm_t net)
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}
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}
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extern "C" ivl_expr_t ivl_lpm_aset_value(ivl_lpm_t net)
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{
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assert(net);
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switch (net->type) {
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case IVL_LPM_FF:
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case IVL_LPM_RAM:
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return net->u_.ff.aset_value;
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default:
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assert(0);
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return 0;
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}
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}
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extern "C" ivl_scope_t ivl_lpm_define(ivl_lpm_t net)
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{
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assert(net);
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@ -1573,6 +1585,10 @@ extern "C" ivl_statement_t ivl_stmt_sub_stmt(ivl_statement_t net)
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/*
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* $Log: t-dll-api.cc,v $
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* Revision 1.88 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.87 2002/09/26 03:18:04 steve
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* Generate vvp code for asynch set/reset of NetFF.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll-expr.cc,v 1.28 2002/08/12 01:35:00 steve Exp $"
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#ident "$Id: t-dll-expr.cc,v 1.29 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "config.h"
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@ -103,6 +103,38 @@ void dll_target::mul_expr_by_const_(long val)
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expr_ = tmps;
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}
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ivl_expr_t dll_target::expr_from_value_(const verinum&val)
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{
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ivl_expr_t expr = (ivl_expr_t)calloc(1, sizeof(struct ivl_expr_s));
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assert(expr);
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unsigned idx;
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char*bits;
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expr->type_ = IVL_EX_NUMBER;
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expr->width_= val.len();
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expr->signed_ = val.has_sign()? 1 : 0;
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expr->u_.number_.bits_ = bits = (char*)malloc(expr->width_);
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for (idx = 0 ; idx < expr->width_ ; idx += 1)
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switch (val.get(idx)) {
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case verinum::V0:
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bits[idx] = '0';
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break;
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case verinum::V1:
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bits[idx] = '1';
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break;
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case verinum::Vx:
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bits[idx] = 'x';
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break;
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case verinum::Vz:
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bits[idx] = 'z';
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break;
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default:
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assert(0);
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}
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return expr;
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}
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void dll_target::expr_binary(const NetEBinary*net)
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{
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assert(expr_ == 0);
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@ -458,6 +490,10 @@ void dll_target::expr_unary(const NetEUnary*net)
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/*
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* $Log: t-dll-expr.cc,v $
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* Revision 1.29 2002/10/23 01:47:17 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.28 2002/08/12 01:35:00 steve
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* conditional ident string using autoconfig.
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*
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13
t-dll.cc
13
t-dll.cc
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll.cc,v 1.96 2002/09/26 03:18:04 steve Exp $"
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#ident "$Id: t-dll.cc,v 1.97 2002/10/23 01:47:18 steve Exp $"
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#endif
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# include "config.h"
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@ -1376,9 +1376,14 @@ void dll_target::lpm_ff(const NetFF*net)
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assert(nex->t_cookie());
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obj->u_.ff.aset = (ivl_nexus_t) nex->t_cookie();
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assert(obj->u_.ff.aset);
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nexus_lpm_add(obj->u_.ff.aclr, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
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nexus_lpm_add(obj->u_.ff.aset, obj, 0, IVL_DR_HiZ, IVL_DR_HiZ);
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verinum tmp = net->aset_value();
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obj->u_.ff.aset_value = expr_from_value_(tmp);
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} else {
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obj->u_.ff.aset = 0;
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obj->u_.ff.aset_value = 0;
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}
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if (obj->u_.ff.width == 1) {
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@ -1974,6 +1979,10 @@ extern const struct target tgt_dll = { "dll", &dll_target_obj };
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/*
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* $Log: t-dll.cc,v $
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* Revision 1.97 2002/10/23 01:47:18 steve
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* Fix synth2 handling of aset/aclr signals where
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* flip-flops are split by begin-end blocks.
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*
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* Revision 1.96 2002/09/26 03:18:04 steve
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* Generate vvp code for asynch set/reset of NetFF.
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*
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|
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9
t-dll.h
9
t-dll.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
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*/
|
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: t-dll.h,v 1.94 2002/09/26 03:18:04 steve Exp $"
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#ident "$Id: t-dll.h,v 1.95 2002/10/23 01:47:17 steve Exp $"
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#endif
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# include "target.h"
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@ -154,6 +154,8 @@ struct dll_target : public target_t, public expr_scan_t {
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void sub_off_from_expr_(long);
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void mul_expr_by_const_(long);
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static ivl_expr_t expr_from_value_(const verinum&that);
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};
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/*
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@ -282,6 +284,7 @@ struct ivl_lpm_s {
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ivl_nexus_t pin;
|
||||
} s;
|
||||
ivl_memory_t mem; // ram only
|
||||
ivl_expr_t aset_value;
|
||||
} ff;
|
||||
|
||||
struct ivl_lpm_mux_s {
|
||||
|
|
@ -619,6 +622,10 @@ struct ivl_statement_s {
|
|||
|
||||
/*
|
||||
* $Log: t-dll.h,v $
|
||||
* Revision 1.95 2002/10/23 01:47:17 steve
|
||||
* Fix synth2 handling of aset/aclr signals where
|
||||
* flip-flops are split by begin-end blocks.
|
||||
*
|
||||
* Revision 1.94 2002/09/26 03:18:04 steve
|
||||
* Generate vvp code for asynch set/reset of NetFF.
|
||||
*
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: stub.c,v 1.69 2002/09/26 03:18:04 steve Exp $"
|
||||
#ident "$Id: stub.c,v 1.70 2002/10/23 01:45:24 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "config.h"
|
||||
|
|
@ -195,9 +195,12 @@ static void show_lpm(ivl_lpm_t net)
|
|||
fprintf(out, " Aclr: %s\n",
|
||||
ivl_nexus_name(ivl_lpm_async_clr(net)));
|
||||
|
||||
if (ivl_lpm_async_set(net))
|
||||
if (ivl_lpm_async_set(net)) {
|
||||
fprintf(out, " Aset: %s\n",
|
||||
ivl_nexus_name(ivl_lpm_async_set(net)));
|
||||
if (ivl_lpm_aset_value(net))
|
||||
show_expression(ivl_lpm_aset_value(net), 10);
|
||||
}
|
||||
|
||||
for (idx = 0 ; idx < width ; idx += 1)
|
||||
fprintf(out, " Data %u: %s\n", idx,
|
||||
|
|
@ -725,6 +728,10 @@ int target_design(ivl_design_t des)
|
|||
|
||||
/*
|
||||
* $Log: stub.c,v $
|
||||
* Revision 1.70 2002/10/23 01:45:24 steve
|
||||
* Fix synth2 handling of aset/aclr signals where
|
||||
* flip-flops are split by begin-end blocks.
|
||||
*
|
||||
* Revision 1.69 2002/09/26 03:18:04 steve
|
||||
* Generate vvp code for asynch set/reset of NetFF.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue