Add support for wide OR/NOR gates.
This commit is contained in:
steve
parent
253f3bc660
commit
03089bdbf3
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex.c,v 1.26 2003/06/26 03:57:05 steve Exp $"
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#ident "$Id: d-virtex.c,v 1.27 2003/06/28 04:18:47 steve Exp $"
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#endif
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# include "device.h"
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@ -163,6 +163,170 @@ void virtex_show_footer(ivl_design_t des)
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edif_print(xnf, edf);
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}
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static void virtex_or_wide(ivl_net_logic_t net)
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{
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edif_cell_t cell_muxcy_l = xilinx_cell_muxcy_l(xlib);
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edif_cell_t cell_muxcy = xilinx_cell_muxcy(xlib);
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edif_cell_t cell_lut4 = xilinx_cell_lut4(xlib);
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edif_cellref_t true_out, false_out;
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edif_cellref_t lut, muxcy, muxcy_down;
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edif_joint_t jnt;
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unsigned idx, inputs, lut4_cnt;
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if (ivl_logic_type(net) == IVL_LO_OR) {
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true_out = edif_cellref_create(edf, cell_1);
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false_out = edif_cellref_create(edf, cell_0);
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} else {
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true_out = edif_cellref_create(edf, cell_0);
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false_out = edif_cellref_create(edf, cell_1);
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}
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inputs = ivl_logic_pins(net) - 1;
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lut4_cnt = (inputs-1)/4;
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for (idx = 0 ; idx < lut4_cnt ; idx += 1) {
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muxcy = edif_cellref_create(edf, cell_muxcy_l);
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lut = edif_cellref_create(edf, cell_lut4);
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edif_cellref_pstring(lut, "INIT", "0001");
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, muxcy, MUXCY_S);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, true_out, 0);
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edif_add_to_joint(jnt, muxcy, MUXCY_DI);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx*4+1+0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx*4+1+1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx*4+1+2));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, idx*4+1+3));
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edif_add_to_joint(jnt, lut, LUT_I3);
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if (idx > 0) {
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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edif_add_to_joint(jnt, muxcy_down, MUXCY_O);
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} else {
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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edif_add_to_joint(jnt, false_out, 0);
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}
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muxcy_down = muxcy;
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}
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muxcy = edif_cellref_create(edf, cell_muxcy);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, true_out, 0);
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edif_add_to_joint(jnt, muxcy, MUXCY_DI);
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, muxcy, MUXCY_CI);
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edif_add_to_joint(jnt, muxcy_down, MUXCY_O);
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switch (ivl_logic_pins(net) - 1 - lut4_cnt*4) {
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case 1:
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lut = edif_cellref_create(edf, xilinx_cell_inv(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+0));
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edif_add_to_joint(jnt, lut, BUF_I);
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break;
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case 2:
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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break;
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case 3:
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lut = edif_cellref_create(edf, xilinx_cell_lut2(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+2));
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edif_add_to_joint(jnt, lut, LUT_I2);
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break;
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case 4:
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lut = edif_cellref_create(edf, cell_lut4);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+0));
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edif_add_to_joint(jnt, lut, LUT_I0);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+1));
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edif_add_to_joint(jnt, lut, LUT_I1);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+2));
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edif_add_to_joint(jnt, lut, LUT_I2);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, lut4_cnt*4+1+3));
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edif_add_to_joint(jnt, lut, LUT_I3);
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break;
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default:
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assert(0);
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}
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jnt = edif_joint_create(edf);
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edif_add_to_joint(jnt, lut, LUT_O);
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edif_add_to_joint(jnt, muxcy, MUXCY_S);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, muxcy, MUXCY_O);
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}
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/*
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* Pick off the cases where there is a Virtex specific implementation
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* that is better then the generic Xilinx implementation. Route the
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* remaining to the base xilinx_logic implementation.
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*/
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void virtex_logic(ivl_net_logic_t net)
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{
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/* Nothing I can do if the user expresses a specific
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opinion. The cellref attribute forces me to let the base
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xilinx_logic take care of it. */
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if (ivl_logic_attr(net, "cellref")) {
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xilinx_logic(net);
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return;
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}
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switch (ivl_logic_type(net)) {
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case IVL_LO_OR:
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case IVL_LO_NOR:
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if (ivl_logic_pins(net) <= 5) {
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xilinx_logic(net);
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} else {
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virtex_or_wide(net);
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}
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break;
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default:
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xilinx_logic(net);
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break;
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}
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}
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void virtex_generic_dff(ivl_lpm_t net)
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{
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unsigned idx;
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@ -665,7 +829,7 @@ const struct device_s d_virtex_edif = {
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virtex_show_footer,
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xilinx_show_scope,
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xilinx_pad,
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xilinx_logic,
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virtex_logic,
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virtex_generic_dff,
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virtex_eq,
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virtex_eq,
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@ -680,6 +844,9 @@ const struct device_s d_virtex_edif = {
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/*
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* $Log: d-virtex.c,v $
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* Revision 1.27 2003/06/28 04:18:47 steve
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* Add support for wide OR/NOR gates.
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*
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* Revision 1.26 2003/06/26 03:57:05 steve
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* Add Xilinx support for A/B MUX devices.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: d-virtex2.c,v 1.15 2003/06/26 03:57:05 steve Exp $"
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#ident "$Id: d-virtex2.c,v 1.16 2003/06/28 04:18:47 steve Exp $"
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#endif
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# include "device.h"
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@ -136,7 +136,7 @@ const struct device_s d_virtex2_edif = {
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virtex_show_footer,
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xilinx_show_scope,
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xilinx_pad,
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xilinx_logic,
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virtex_logic,
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virtex_generic_dff,
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virtex_eq,
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virtex_eq,
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@ -151,6 +151,9 @@ const struct device_s d_virtex2_edif = {
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/*
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* $Log: d-virtex2.c,v $
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* Revision 1.16 2003/06/28 04:18:47 steve
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* Add support for wide OR/NOR gates.
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*
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* Revision 1.15 2003/06/26 03:57:05 steve
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* Add Xilinx support for A/B MUX devices.
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*
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@ -17,7 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.c,v 1.3 2003/06/26 03:57:05 steve Exp $"
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#ident "$Id: xilinx.c,v 1.4 2003/06/28 04:18:47 steve Exp $"
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#endif
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# include "edif.h"
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@ -52,6 +52,18 @@ edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib)
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return cell;
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}
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edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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if (cell) return cell;
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cell = edif_xcell_create(xlib, "BUFT", 3);
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edif_cell_portconfig(cell, BUF_O, "O", IVL_SIP_OUTPUT);
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edif_cell_portconfig(cell, BUF_I, "I", IVL_SIP_INPUT);
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edif_cell_portconfig(cell, BUF_T, "T", IVL_SIP_INPUT);
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return cell;
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}
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edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib)
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{
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static edif_cell_t cell = 0;
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@ -436,6 +448,24 @@ void xilinx_logic(ivl_net_logic_t net)
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edif_add_to_joint(jnt, obj, BUF_I);
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break;
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case IVL_LO_BUFIF0:
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/* The Xilinx BUFT devices is a BUF that adds a T
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input. The output is tri-stated if the T input is
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1. In other words, it acts just like bufif0. */
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assert(ivl_logic_pins(net) == 3);
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obj = edif_cellref_create(edf, xilinx_cell_buft(xlib));
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 0));
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edif_add_to_joint(jnt, obj, BUF_O);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 1));
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edif_add_to_joint(jnt, obj, BUF_I);
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jnt = edif_joint_of_nexus(edf, ivl_logic_pin(net, 2));
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edif_add_to_joint(jnt, obj, BUF_T);
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break;
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case IVL_LO_NOT:
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assert(ivl_logic_pins(net) == 2);
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@ -732,6 +762,9 @@ void xilinx_shiftl(ivl_lpm_t net)
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/*
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* $Log: xilinx.c,v $
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* Revision 1.4 2003/06/28 04:18:47 steve
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* Add support for wide OR/NOR gates.
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*
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* Revision 1.3 2003/06/26 03:57:05 steve
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* Add Xilinx support for A/B MUX devices.
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*
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: xilinx.h,v 1.3 2003/06/26 03:57:05 steve Exp $"
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#ident "$Id: xilinx.h,v 1.4 2003/06/28 04:18:47 steve Exp $"
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#endif
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/*
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@ -39,12 +39,14 @@
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this category. */
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extern edif_cell_t xilinx_cell_buf (edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_bufg(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_buft(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_inv (edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_ibuf(edif_xlibrary_t xlib);
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extern edif_cell_t xilinx_cell_obuf(edif_xlibrary_t xlib);
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#define BUF_O 0
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#define BUF_I 1
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/* Only some buffers have this input. */
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#define BUF_T 2
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/* === LUT Devices === */
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@ -96,6 +98,7 @@ extern edif_cell_t xilinx_cell_xorcy(edif_xlibrary_t xlib);
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/* === Inheritable Methods === */
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extern void virtex_show_footer(ivl_design_t des);
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extern void virtex_logic(ivl_net_logic_t net);
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extern void virtex_generic_dff(ivl_lpm_t net);
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extern void virtex_eq(ivl_lpm_t net);
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extern void virtex_ge(ivl_lpm_t net);
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@ -110,6 +113,9 @@ extern void xilinx_shiftl(ivl_lpm_t net);
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/*
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* $Log: xilinx.h,v $
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* Revision 1.4 2003/06/28 04:18:47 steve
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* Add support for wide OR/NOR gates.
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*
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* Revision 1.3 2003/06/26 03:57:05 steve
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* Add Xilinx support for A/B MUX devices.
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*
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