Add new virtex2 architecture family, and
also the new edif.h EDIF management functions.
This commit is contained in:
steve
parent
20c0d8f3ba
commit
ff032fa18c
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@ -16,7 +16,7 @@
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# 59 Temple Place - Suite 330
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# Boston, MA 02111-1307, USA
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#
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#ident "$Id: Makefile.in,v 1.7 2003/02/27 22:13:22 steve Exp $"
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#ident "$Id: Makefile.in,v 1.8 2003/03/24 00:47:54 steve Exp $"
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#
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#
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SHELL = /bin/sh
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@ -52,8 +52,8 @@ dep:
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$(CC) -Wall @ident_support@ -I$(srcdir)/.. $(CPPFLAGS) -MD -c $< -o $*.o
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mv $*.d dep
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D = d-generic.o d-generic-edif.o d-virtex.o
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O = fpga.o gates.o mangle.o tables.o $D
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D = d-generic.o d-generic-edif.o d-virtex.o d-virtex2.o
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O = edif.o fpga.o gates.o mangle.o tables.o $D
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ifeq (@WIN32@,yes)
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TGTLDFLAGS=-L.. -livl
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,435 @@
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/*
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* Copyright (c) 200Stephen Williams (steve@icarus.com)
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifdef HAVE_CVS_IDENT
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#ident "$Id: edif.c,v 1.1 2003/03/24 00:47:54 steve Exp $"
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#endif
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# include "edif.h"
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# include <stdlib.h>
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# include <string.h>
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#ifdef HAVE_MALLOC_H
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# include <malloc.h>
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#endif
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# include <assert.h>
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struct cellref_property_ {
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const char*name;
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const char*value;
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struct cellref_property_*next;
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};
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struct edif_s {
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const char*name;
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/* List the ports of the design. */
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unsigned nports;
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struct __cell_port*ports;
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/* All the external libraries attached to me. */
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edif_xlibrary_t xlibs;
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/* list the cellref instances. */
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edif_cellref_t celref;
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/* The root instance has cellref properties as well. */
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struct cellref_property_*property;
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/* Keep a list of all the nexa */
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struct edif_joint_s*nexa;
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};
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struct edif_xlibrary_s {
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/* Name of this library. */
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const char*name;
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/* The cells that are contained in this library. */
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struct edif_cell_s*cells;
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/* used to list libraries in an edif_t. */
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struct edif_xlibrary_s*next;
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};
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struct __cell_port {
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const char*name;
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ivl_signal_port_t dir;
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};
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struct edif_cell_s {
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const char*name;
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edif_xlibrary_t xlib;
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unsigned nports;
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struct __cell_port*ports;
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struct edif_cell_s*next;
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};
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struct edif_cellref_s {
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struct edif_cell_s* cell;
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unsigned u;
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struct cellref_property_*property;
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struct edif_cellref_s* next;
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};
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struct joint_cell_ {
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struct edif_cellref_s*cell;
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unsigned port;
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struct joint_cell_*next;
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};
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struct edif_joint_s {
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struct joint_cell_*links;
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struct edif_joint_s*next;
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};
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edif_t edif_create(const char*design_name, unsigned nports)
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{
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edif_t edf = malloc(sizeof(struct edif_s));
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edf->name = design_name;
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edf->nports= nports;
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edf->ports = nports? calloc(nports, sizeof(struct __cell_port)) : 0;
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edf->celref= 0;
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edf->xlibs = 0;
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edf->property = 0;
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edf->nexa = 0;
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return edf;
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}
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void edif_portconfig(edif_t edf, unsigned idx,
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const char*name, ivl_signal_port_t dir)
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{
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assert(idx < edf->nports);
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edf->ports[idx].name = name;
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edf->ports[idx].dir = dir;
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}
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void edif_port_to_joint(edif_joint_t jnt, edif_t edf, unsigned port)
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{
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struct joint_cell_* jc = malloc(sizeof(struct joint_cell_));
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jc->cell = 0;
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jc->port = port;
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jc->next = jnt->links;
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jnt->links = jc;
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}
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void edif_pstring(edif_t edf, const char*name, const char*value)
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{
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struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
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prp->name = name;
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prp->value = value;
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prp->next = edf->property;
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edf->property = prp;
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}
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edif_xlibrary_t edif_xlibrary_create(edif_t edf, const char*name)
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{
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edif_xlibrary_t xlib = malloc(sizeof(struct edif_xlibrary_s));
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xlib->name = name;
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xlib->cells= 0;
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xlib->next = edf->xlibs;
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edf->xlibs = xlib;
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return xlib;
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}
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edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t xlib,
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const char*cell_name)
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{
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edif_cell_t cur;
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for (cur = xlib->cells ; cur ; cur = cur->next) {
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if (strcmp(cell_name, cur->name) == 0)
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return cur;
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}
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return 0;
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}
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edif_cell_t edif_xcell_create(edif_xlibrary_t xlib, const char*name,
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unsigned nports)
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{
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unsigned idx;
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edif_cell_t cell = malloc(sizeof(struct edif_cell_s));
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cell->name = name;
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cell->xlib = xlib;
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cell->nports = nports;
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cell->ports = calloc(nports, sizeof(struct __cell_port));
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for (idx = 0 ; idx < nports ; idx += 1) {
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cell->ports[idx].name = "?";
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cell->ports[idx].dir = IVL_SIP_NONE;
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}
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cell->next = xlib->cells;
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xlib->cells = cell;
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return cell;
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}
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void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
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const char*name, ivl_signal_port_t dir)
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{
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assert(idx < cell->nports);
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cell->ports[idx].name = name;
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cell->ports[idx].dir = dir;
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}
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unsigned edif_cell_port_byname(edif_cell_t cell, const char*name)
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{
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unsigned idx = 0;
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for (idx = 0 ; idx < cell->nports ; idx += 1)
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if (strcmp(name, cell->ports[idx].name) == 0)
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break;
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return idx;
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}
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edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell)
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{
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static unsigned u_number = 0;
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edif_cellref_t ref = malloc(sizeof(struct edif_cellref_s));
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u_number += 1;
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assert(cell);
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assert(edf);
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ref->u = u_number;
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ref->cell = cell;
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ref->property = 0;
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ref->next = edf->celref;
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edf->celref = ref;
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return ref;
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}
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void edif_cellref_pstring(edif_cellref_t ref, const char*name,
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const char*value)
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{
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struct cellref_property_*prp = malloc(sizeof(struct cellref_property_));
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prp->name = name;
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prp->value = value;
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prp->next = ref->property;
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ref->property = prp;
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}
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edif_joint_t edif_joint_create(edif_t edf)
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{
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edif_joint_t jnt = malloc(sizeof(struct edif_joint_s));
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jnt->links = 0;
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jnt->next = edf->nexa;
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edf->nexa = jnt;
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return jnt;
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}
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edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex)
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{
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void*tmp = ivl_nexus_get_private(nex);
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edif_joint_t jnt;
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if (tmp == 0) {
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jnt = edif_joint_create(edf);
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ivl_nexus_set_private(nex, jnt);
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return jnt;
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}
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jnt = (edif_joint_t) tmp;
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return jnt;
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}
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void edif_add_to_joint(edif_joint_t jnt, edif_cellref_t cell, unsigned port)
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{
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struct joint_cell_* jc = malloc(sizeof(struct joint_cell_));
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jc->cell = cell;
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jc->port = port;
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jc->next = jnt->links;
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jnt->links = jc;
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}
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/*
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* This function takes all the data structures that have been
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* assembled by the code generator, and writes them into an EDIF
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* formatted file.
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*/
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void edif_print(FILE*fd, edif_t edf)
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{
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edif_xlibrary_t xlib;
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edif_cell_t cell;
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edif_cellref_t ref;
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edif_joint_t jnt;
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struct cellref_property_*prp;
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unsigned idx;
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fprintf(fd, "(edif %s\n", edf->name);
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fprintf(fd, " (edifVersion 2 0 0)\n");
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fprintf(fd, " (edifLevel 0)\n");
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fprintf(fd, " (keywordMap (keywordLevel 0))\n");
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fprintf(fd, " (status\n");
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fprintf(fd, " (written\n");
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fprintf(fd, " (timeStamp 0 0 0 0 0 0)\n");
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fprintf(fd, " (author \"unknown\")\n");
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fprintf(fd, " (program \"Icarus Verilog/fpga.tgt\")))\n");
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fflush(fd);
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for (xlib = edf->xlibs ; xlib ; xlib = xlib->next) {
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fprintf(fd, " (external %s "
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"(edifLevel 0) "
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"(technology (numberDefinition))\n",
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xlib->name);
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for (cell = xlib->cells ; cell ; cell = cell->next) {
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fprintf(fd, " (cell %s (cellType GENERIC)\n",
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cell->name);
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fprintf(fd, " (view net\n"
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" (viewType NETLIST)\n"
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" (interface");
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for (idx = 0 ; idx < cell->nports ; idx += 1) {
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struct __cell_port*pp = cell->ports + idx;
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fprintf(fd, "\n (port %s", pp->name);
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switch (pp->dir) {
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case IVL_SIP_INPUT:
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fprintf(fd, " (direction INPUT)");
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break;
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case IVL_SIP_OUTPUT:
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fprintf(fd, " (direction OUTPUT)");
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break;
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case IVL_SIP_INOUT:
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fprintf(fd, " (direction INOUT)");
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break;
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default:
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break;
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}
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fprintf(fd, ")");
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}
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fprintf(fd, ")))\n");
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}
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fprintf(fd, " )\n"); /* terminate (external ...) sexp */
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}
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fflush(fd);
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/* Write out the library header */
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fprintf(fd, " (library DESIGN\n");
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fprintf(fd, " (edifLevel 0)\n");
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fprintf(fd, " (technology (numberDefinition))\n");
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/* The root module is a cell in the library. */
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fprintf(fd, " (cell %s\n", edf->name);
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fprintf(fd, " (cellType GENERIC)\n");
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fprintf(fd, " (view net\n");
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fprintf(fd, " (viewType NETLIST)\n");
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fprintf(fd, " (interface\n");
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for (idx = 0 ; idx < edf->nports ; idx += 1) {
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fprintf(fd, " (port %s ", edf->ports[idx].name);
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switch (edf->ports[idx].dir) {
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case IVL_SIP_INPUT:
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fprintf(fd, "(direction INPUT)");
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break;
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case IVL_SIP_OUTPUT:
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fprintf(fd, "(direction OUTPUT)");
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break;
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case IVL_SIP_INOUT:
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fprintf(fd, "(direction INOUT)");
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break;
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default:
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break;
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}
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fprintf(fd, ")\n");
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}
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fprintf(fd, " )\n"); /* end the (interface ) sexp */
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fflush(fd);
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fprintf(fd, " (contents\n");
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/* Display all the instances. */
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for (ref = edf->celref ; ref ; ref = ref->next) {
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assert(ref->cell);
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fprintf(fd, "(instance U%u (viewRef net "
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"(cellRef %s (libraryRef %s)))",
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ref->u, ref->cell->name, ref->cell->xlib->name);
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for (prp = ref->property ; prp ; prp = prp->next)
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fprintf(fd, " (property %s (string \"%s\"))",
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prp->name, prp->value);
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fprintf(fd, ")\n");
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}
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fflush(fd);
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/* Display all the joints. */
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idx = 0;
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for (jnt = edf->nexa ; jnt ; jnt = jnt->next, idx += 1) {
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struct joint_cell_*jc;
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fprintf(fd, "(net N%u (joined", idx);
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for (jc = jnt->links ; jc ; jc = jc->next) {
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if (jc->cell)
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fprintf(fd, " (portRef %s (instanceRef U%u))",
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jc->cell->cell->ports[jc->port].name,
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jc->cell->u);
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else
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fprintf(fd, " (portRef %s)",
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edf->ports[jc->port].name);
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}
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fprintf(fd, "))\n");
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}
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fprintf(fd, " )\n"); /* end the (contents...) sexp */
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fprintf(fd, " )\n"); /* end the (view ) sexp */
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fprintf(fd, " )\n"); /* end the (cell ) sexp */
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fprintf(fd, " )\n"); /* end the (library DESIGN) sexp */
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/* Make an instance of the defined object */
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fprintf(fd, " (design %s\n", edf->name);
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fprintf(fd, " (cellRef %s (libraryRef DESIGN))\n", edf->name);
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for (prp = edf->property ; prp ; prp = prp->next) {
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fprintf(fd, " (property %s (string \"%s\"))\n",
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prp->name, prp->value);
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}
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fprintf(fd, " )\n");
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fprintf(fd, ")\n");
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fflush(fd);
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}
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/*
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* $Log: edif.c,v $
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* Revision 1.1 2003/03/24 00:47:54 steve
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* Add new virtex2 architecture family, and
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* also the new edif.h EDIF management functions.
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*
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*/
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@ -0,0 +1,201 @@
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#ifndef __edif_H
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#define __edif_H
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/*
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* Copyright (c) 2003 Stephen Williams (steve@icarus.com)
|
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*
|
||||
* This source code is free software; you can redistribute it
|
||||
* and/or modify it in source code form under the terms of the GNU
|
||||
* General Public License as published by the Free Software
|
||||
* Foundation; either version 2 of the License, or (at your option)
|
||||
* any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: edif.h,v 1.1 2003/03/24 00:47:54 steve Exp $"
|
||||
#endif
|
||||
|
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# include <stdio.h>
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# include <ivl_target.h>
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|
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/*
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* These types and functions support the task of generating and
|
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* writing out an EDIF 2 0 0 netlist. These functions work by
|
||||
* supporting the creation of an in-core netlist of the design, then
|
||||
* writing the netlist out all at once. The library manages cells with
|
||||
* ports, but does not otherwise interpret cells. They have no
|
||||
* contents.
|
||||
*
|
||||
* The general structure of netlist creation is as follows:
|
||||
*
|
||||
* Create a netlist with edif_create(<name>);
|
||||
* This creates an edif object that represents the design. The
|
||||
* design is given a name, and that name becomes the name of the
|
||||
* single cell that this netlist handles.
|
||||
*
|
||||
* Add ports to the root with edif_portconfig
|
||||
* The design may, if it is a macro to be included in a larger
|
||||
* design, include ports. These are discovered by looking for port
|
||||
* signals in the root module.
|
||||
*
|
||||
* Declare external libraries with edif_xlibrary_create
|
||||
* Normally, this is the single technology library that contains
|
||||
* the primitive cells that the code generator intendes to
|
||||
* use. The library is given a name, such as VIRTEX or whatever
|
||||
* the implementation tools expect. Cells are attached to the
|
||||
* library later. An edif netlist may include multiple external
|
||||
* references.
|
||||
*
|
||||
* Declare primitives with edif_xcell_create and edif_cell_portconfig.
|
||||
* These functions create CELL TYPES that are attached to an
|
||||
* external library. The libraries are created by
|
||||
* edif_xlibrary_create.
|
||||
*
|
||||
* Cells can be created at any time before their first use. It
|
||||
* therefore makes the most sense to not create the cell until it
|
||||
* is certain that they are needed by the design.
|
||||
*
|
||||
* Create instances and join them up
|
||||
* The edif_cellref_t objects represent instances of cells, and
|
||||
* are the devices of the generated netlist. These cellrefs are
|
||||
* connected together by the use of edif_joint_t joints. The
|
||||
* joints can be created from ivl_nexus_t objects, or from their
|
||||
* own ether. This instantiating of cells and joining them
|
||||
* together that is the most fun. It is the technology specific
|
||||
* stuff that the code generator does.
|
||||
*
|
||||
* Finally, print the result with edif_print(fd);
|
||||
* This function writes the netlist in memory to an EDIF file on
|
||||
* the stdio stream specified.
|
||||
*
|
||||
* This library is intended to be used once, to build up a netlist and
|
||||
* print it. All the names that are taken as const char* should be
|
||||
* somehow made permanent by the caller. Either they are constant
|
||||
* strings, or they are strduped as necessary to make them
|
||||
* permanent. The library will not duplicate them.
|
||||
*/
|
||||
|
||||
/* TYPE DECLARATIONS */
|
||||
|
||||
/* This represents the entire EDIF design. You only need one of these
|
||||
to hold everything. */
|
||||
typedef struct edif_s* edif_t;
|
||||
|
||||
/* Each external library of the design gets one of these. */
|
||||
typedef struct edif_xlibrary_s* edif_xlibrary_t;
|
||||
|
||||
/* This represents a type of cell. */
|
||||
typedef struct edif_cell_s* edif_cell_t;
|
||||
|
||||
/* A cellref is an *instance* of a cell. */
|
||||
typedef struct edif_cellref_s* edif_cellref_t;
|
||||
|
||||
/* This represents a generic joint. Cell ports are connected by being
|
||||
associated with a joint. These can be bound to an ivl_nexus_t
|
||||
object, of stand along. */
|
||||
typedef struct edif_joint_s* edif_joint_t;
|
||||
|
||||
|
||||
/* FUNCTIONS */
|
||||
|
||||
|
||||
/* Start a new EDIF design. The design_name will be used as the name
|
||||
of the top-mode module of the design. */
|
||||
extern edif_t edif_create(const char*design_name, unsigned nports);
|
||||
|
||||
/* macro ports to the design are handled by this library similar to
|
||||
cells. The user creates ports with this function. This function
|
||||
configures the sole "port" of the cell with the name and dir passed
|
||||
in. The direction, in this case, is the *interface* direction. */
|
||||
extern void edif_portconfig(edif_t edf, unsigned idx,
|
||||
const char*name, ivl_signal_port_t dir);
|
||||
|
||||
/* This is like edif_add_to_joint, but works with the edif port. */
|
||||
extern void edif_port_to_joint(edif_joint_t jnt, edif_t edf, unsigned port);
|
||||
|
||||
/* The design may have properties attached to it. These properties
|
||||
will be attached to the instance declared in the footer of the EDIF
|
||||
file. */
|
||||
extern void edif_pstring(edif_t edf, const char*name, const char*value);
|
||||
|
||||
/* Create an external library and attach it to the edif design. This
|
||||
will lead to a (external ...) declaration of cells that can be used
|
||||
by the design. */
|
||||
extern edif_xlibrary_t edif_xlibrary_create(edif_t edf, const char*name);
|
||||
|
||||
/* External libraries can be searched for existing cells, given a
|
||||
string name. This function searches for the cell by name, and
|
||||
returns it. */
|
||||
extern edif_cell_t edif_xlibrary_findcell(edif_xlibrary_t lib,
|
||||
const char*cell_name);
|
||||
|
||||
/* Create a new cell, attached to the external library. Specify the
|
||||
number of ports that the cell has. The edif_cell_portconfig
|
||||
function is then used to assign name and direction to each of the
|
||||
ports.
|
||||
|
||||
The cell has a number of pins that are referenced by their number
|
||||
from 0 to nports-1. You need to remember the pin numbers for the
|
||||
named ports for use when joining that pin to an edif_joint_t.
|
||||
|
||||
Cellrefs get their port characteristics from the cell that they are
|
||||
created from. So the pinouts of cellrefs match the pinout of the
|
||||
associated cell. */
|
||||
extern edif_cell_t edif_xcell_create(edif_xlibrary_t, const char*name,
|
||||
unsigned nports);
|
||||
extern void edif_cell_portconfig(edif_cell_t cell, unsigned idx,
|
||||
const char*name, ivl_signal_port_t dir);
|
||||
|
||||
/* Ports of cells are normally referenced by their port number. If you
|
||||
forget what that number is, this function can look it up by name. */
|
||||
extern unsigned edif_cell_port_byname(edif_cell_t cell, const char*name);
|
||||
|
||||
|
||||
/* Create and instance from a cell. The instance refers to the cell,
|
||||
which is a type, and contains pips for pins. */
|
||||
extern edif_cellref_t edif_cellref_create(edif_t edf, edif_cell_t cell);
|
||||
|
||||
/* Instances can have properties attached to them. The name and value
|
||||
given here are turned into a (property <name> (string "val"))
|
||||
sexpression attached to the instance.
|
||||
|
||||
Examples of string properties commonly attached to cellref devices
|
||||
include such things as the INIT=<value> to initialize LUT cells in
|
||||
FPGA devices. */
|
||||
extern void edif_cellref_pstring(edif_cellref_t ref, const char*name,
|
||||
const char*value);
|
||||
|
||||
/* This function gets the joint associated with a nexus. This will
|
||||
create a joint if necessary. */
|
||||
extern edif_joint_t edif_joint_of_nexus(edif_t edf, ivl_nexus_t nex);
|
||||
|
||||
/* For linking cells outside the ivl netlist, this function creates an
|
||||
anonymous joint. */
|
||||
extern edif_joint_t edif_joint_create(edif_t edf);
|
||||
|
||||
/* Given a joint, this function adds the cell reference. */
|
||||
extern void edif_add_to_joint(edif_joint_t jnt,
|
||||
edif_cellref_t cell,
|
||||
unsigned port);
|
||||
|
||||
/*
|
||||
* Print the entire design. This should only be done after the design
|
||||
* is completely assembled.
|
||||
*/
|
||||
extern void edif_print(FILE*fd, edif_t design);
|
||||
|
||||
/*
|
||||
* $Log: edif.h,v $
|
||||
* Revision 1.1 2003/03/24 00:47:54 steve
|
||||
* Add new virtex2 architecture family, and
|
||||
* also the new edif.h EDIF management functions.
|
||||
*
|
||||
*/
|
||||
#endif
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
FPGA LOADABLE CODE GENERATOR FOR Icarus Verilog
|
||||
|
||||
Copyright 2001 Stephen Williams
|
||||
$Id: fpga.txt,v 1.5 2002/04/30 04:26:42 steve Exp $
|
||||
$Id: fpga.txt,v 1.6 2003/03/24 00:47:54 steve Exp $
|
||||
|
||||
The FPGA code generator supports a variety of FPGA devices, writing
|
||||
XNF or EDIF depending on the target. You can select the architecture
|
||||
|
|
@ -51,6 +51,11 @@ should work properly for any Virtex part.
|
|||
|
||||
XNF ROOT PORTS
|
||||
|
||||
NOTE: As parts are moved over to EDIF format, XNF support will be
|
||||
phased out. Current Xilinx implementation tools will accept EDIF
|
||||
format files even for the older parts, and non-Xilinx implementation
|
||||
tools accept nothing else.
|
||||
|
||||
When the output format is XNF, the code generator will generate "SIG"
|
||||
records for the signals that are ports of the root module. The name is
|
||||
declared as an external pin that this macro makes available.
|
||||
|
|
@ -169,6 +174,10 @@ Compile a single-file design with command line tools like so:
|
|||
|
||||
---
|
||||
$Log: fpga.txt,v $
|
||||
Revision 1.6 2003/03/24 00:47:54 steve
|
||||
Add new virtex2 architecture family, and
|
||||
also the new edif.h EDIF management functions.
|
||||
|
||||
Revision 1.5 2002/04/30 04:26:42 steve
|
||||
Spelling errors.
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,7 @@
|
|||
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
|
||||
*/
|
||||
#ifdef HAVE_CVS_IDENT
|
||||
#ident "$Id: tables.c,v 1.4 2002/08/12 01:35:03 steve Exp $"
|
||||
#ident "$Id: tables.c,v 1.5 2003/03/24 00:47:54 steve Exp $"
|
||||
#endif
|
||||
|
||||
# include "fpga_priv.h"
|
||||
|
|
@ -27,6 +27,7 @@
|
|||
extern const struct device_s d_generic;
|
||||
extern const struct device_s d_generic_edif;
|
||||
extern const struct device_s d_virtex_edif;
|
||||
extern const struct device_s d_virtex2_edif;
|
||||
|
||||
|
||||
const struct device_table_s {
|
||||
|
|
@ -36,6 +37,7 @@ const struct device_table_s {
|
|||
{ "generic-edif", &d_generic_edif },
|
||||
{ "generic-xnf", &d_generic },
|
||||
{ "virtex", &d_virtex_edif },
|
||||
{ "virtex2", &d_virtex2_edif },
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
|
@ -56,6 +58,10 @@ device_t device_from_arch(const char*arch)
|
|||
|
||||
/*
|
||||
* $Log: tables.c,v $
|
||||
* Revision 1.5 2003/03/24 00:47:54 steve
|
||||
* Add new virtex2 architecture family, and
|
||||
* also the new edif.h EDIF management functions.
|
||||
*
|
||||
* Revision 1.4 2002/08/12 01:35:03 steve
|
||||
* conditional ident string using autoconfig.
|
||||
*
|
||||
|
|
|
|||
Loading…
Reference in New Issue