synth_asych of if/else requires redirecting the target
if sub-statements. Use NetNet objects to manage the situation.
This commit is contained in:
steve
parent
3595b6d186
commit
d5e9e13555
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@ -17,11 +17,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT)
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#ident "$Id: net_nex_output.cc,v 1.1 2002/06/30 02:21:32 steve Exp $"
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#endif
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#if !defined(WINNT)
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#ident "$Id: net_nex_output.cc,v 1.1 2002/06/30 02:21:32 steve Exp $"
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#ident "$Id: net_nex_output.cc,v 1.2 2002/07/01 00:54:21 steve Exp $"
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#endif
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# include "config.h"
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@ -40,23 +36,38 @@ void NetProc::nex_output(NexusSet&out)
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<< endl;
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}
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void NetAssign::nex_output(NexusSet&out)
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void NetAssignBase::nex_output(NexusSet&out)
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{
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cerr << get_line()
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<< ": internal error: NetProc::nex_output not implemented"
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<< endl;
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NetNet*lsig = lval_->sig();
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assert(lsig);
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assert(lval_->more == 0);
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for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
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out.add(lsig->pin(idx).nexus());
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}
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void NetCondit::nex_output(NexusSet&out)
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{
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cerr << get_line()
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<< ": internal error: NetProc::nex_output not implemented"
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<< endl;
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if (if_ != 0)
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if_->nex_output(out);
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if (else_ != 0)
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else_->nex_output(out);
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}
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void NetEvWait::nex_output(NexusSet&out)
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{
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assert(statement_);
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statement_->nex_output(out);
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}
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/*
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* $Log: net_nex_output.cc,v $
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* Revision 1.2 2002/07/01 00:54:21 steve
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* synth_asych of if/else requires redirecting the target
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* if sub-statements. Use NetNet objects to manage the
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* situation.
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*
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* Revision 1.1 2002/06/30 02:21:32 steve
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* Add structure for asynchronous logic synthesis.
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*
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27
netlist.h
27
netlist.h
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@ -19,7 +19,7 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: netlist.h,v 1.248 2002/06/30 02:21:32 steve Exp $"
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#ident "$Id: netlist.h,v 1.249 2002/07/01 00:54:21 steve Exp $"
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#endif
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/*
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@ -1204,7 +1204,8 @@ class NetProc : public LineInfo {
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virtual bool is_asynchronous();
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// synthesize as asynchronous logic, and return true.
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virtual bool synth_async(Design*, NetScope*scope);
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virtual bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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virtual void dump(ostream&, unsigned ind) const;
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@ -1312,12 +1313,15 @@ class NetAssignBase : public NetProc {
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const NetExpr* get_delay() const;
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virtual NexusSet* nex_input();
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virtual void nex_output(NexusSet&o);
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// This returns the total width of the accumulated l-value. It
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// accounts for any grouping of NetAssign_ objects that might happen.
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unsigned lwidth() const;
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bool synth_async(Design*des, NetScope*scope);
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bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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// This dumps all the lval structures.
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void dump_lval(ostream&) const;
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@ -1336,8 +1340,6 @@ class NetAssign : public NetAssignBase {
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bool is_asynchronous();
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void nex_output(NexusSet&o);
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virtual bool emit_proc(struct target_t*) const;
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virtual int match_proc(struct proc_match_t*);
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virtual void dump(ostream&, unsigned ind) const;
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@ -1503,7 +1505,8 @@ class NetCondit : public NetProc {
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virtual void nex_output(NexusSet&o);
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bool is_asynchronous();
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bool synth_async(Design*des, NetScope*scope);
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bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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virtual bool emit_proc(struct target_t*) const;
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virtual int match_proc(struct proc_match_t*);
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@ -1626,6 +1629,8 @@ class NetEvent : public LineInfo {
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NetScope* scope();
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const NetScope* scope() const;
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void nex_output(NexusSet&);
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// Locate the first event that matches my behavior and
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// monitors the same signals.
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NetEvent* find_similar_event();
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@ -1708,7 +1713,10 @@ class NetEvWait : public NetProc {
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// process. This method checks.
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virtual bool is_asynchronous();
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virtual bool synth_async(Design*des, NetScope*scope);
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virtual void nex_output(NexusSet&out);
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virtual bool synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out);
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virtual void dump(ostream&, unsigned ind) const;
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@ -2985,6 +2993,11 @@ extern ostream& operator << (ostream&, NetNet::Type);
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/*
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* $Log: netlist.h,v $
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* Revision 1.249 2002/07/01 00:54:21 steve
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* synth_asych of if/else requires redirecting the target
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* if sub-statements. Use NetNet objects to manage the
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* situation.
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*
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* Revision 1.248 2002/06/30 02:21:32 steve
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* Add structure for asynchronous logic synthesis.
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*
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112
synth2.cc
112
synth2.cc
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@ -17,54 +17,123 @@
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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#if !defined(WINNT) && !defined(macintosh)
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#ident "$Id: synth2.cc,v 1.1 2002/06/30 02:21:32 steve Exp $"
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#ident "$Id: synth2.cc,v 1.2 2002/07/01 00:54:21 steve Exp $"
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#endif
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# include "config.h"
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# include "functor.h"
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# include "netlist.h"
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# include "compiler.h"
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# include <assert.h>
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static unsigned find_nexus_in_set(const NetNet*nset, const Nexus*nex)
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{
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unsigned idx = 0;
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for (idx = 0 ; idx < nset->pin_count() ; idx += 1)
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if (nset->pin(idx).nexus() == nex)
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return idx;
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return idx;
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}
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/*
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* Async synthesis of assignments is done by synthesizing the rvalue
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* expression, then connecting the l-value directly to the output of
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* the r-value.
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*
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* The nex_map is the O-set for the statement, and lists the positions
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* of the outputs as the caller wants results linked up. The nex_out,
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* however, is the set of nexa that are to actually get linked to the
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* r-value.
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*/
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bool NetAssignBase::synth_async(Design*des, NetScope*scope)
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bool NetAssignBase::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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NetNet*rsig = rval_->synthesize(des);
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assert(rsig);
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NetNet*lsig = lval_->sig();
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assert(lsig);
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assert(lval_->more == 0);
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assert(nex_map->pin_count() == rsig->pin_count());
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assert(lsig->pin_count() == rsig->pin_count());
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for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1)
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connect(lsig->pin(idx), rsig->pin(idx));
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for (unsigned idx = 0 ; idx < lsig->pin_count() ; idx += 1) {
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unsigned ptr = find_nexus_in_set(nex_map, lsig->pin(idx).nexus());
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connect(nex_out->pin(ptr), rsig->pin(idx));
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}
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return true;
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}
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bool NetCondit::synth_async(Design*des, NetScope*scope)
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bool NetCondit::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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return false;
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NetNet*ssig = expr_->synthesize(des);
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assert(ssig);
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assert(if_ != 0);
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assert(else_ != 0);
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NetNet*asig = new NetNet(scope, scope->local_hsymbol(),
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NetNet::WIRE, nex_map->pin_count());
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asig->local_flag(true);
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if_->synth_async(des, scope, nex_map, asig);
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NetNet*bsig = new NetNet(scope, scope->local_hsymbol(),
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NetNet::WIRE, nex_map->pin_count());
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bsig->local_flag(true);
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else_->synth_async(des, scope, nex_map, bsig);
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NetMux*mux = new NetMux(scope, scope->local_hsymbol(),
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nex_out->pin_count(), 2, 1);
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connect(mux->pin_Sel(0), ssig->pin(0));
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for (unsigned idx = 0 ; idx < asig->pin_count() ; idx += 1)
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connect(mux->pin_Data(idx, 1), asig->pin(idx));
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for (unsigned idx = 0 ; idx < bsig->pin_count() ; idx += 1)
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connect(mux->pin_Data(idx, 0), bsig->pin(idx));
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for (unsigned idx = 0 ; idx < mux->width() ; idx += 1)
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connect(nex_out->pin(idx), mux->pin_Result(idx));
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des->add_node(mux);
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return true;
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}
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bool NetEvWait::synth_async(Design*des, NetScope*scope)
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bool NetEvWait::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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return statement_->synth_async(des, scope);
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return statement_->synth_async(des, scope, nex_map, nex_out);
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}
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bool NetProc::synth_async(Design*des, NetScope*scope)
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bool NetProc::synth_async(Design*des, NetScope*scope,
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const NetNet*nex_map, NetNet*nex_out)
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{
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return false;
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}
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bool NetProcTop::synth_async(Design*des)
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{
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return statement_->synth_async(des, scope());
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NexusSet nex_set;
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statement_->nex_output(nex_set);
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NetNet*nex_out = new NetNet(scope(), "tmp", NetNet::WIRE,
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nex_set.count());
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for (unsigned idx = 0 ; idx < nex_out->pin_count() ; idx += 1)
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connect(nex_set[idx], nex_out->pin(idx));
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bool flag = statement_->synth_async(des, scope(), nex_out, nex_out);
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delete nex_out;
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return flag;
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}
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class synth2_f : public functor_t {
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@ -77,18 +146,26 @@ class synth2_f : public functor_t {
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/*
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* Look at a process, and divide the problem into always and initial
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* threads.
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* Look at a process. If it is asynchronous, then synthesize it as an
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* asynchronous process and delete the process itself for its gates.
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*/
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void synth2_f::process(class Design*des, class NetProcTop*top)
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{
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if (! top->is_asynchronous())
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if (! top->is_asynchronous()) {
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if (top->attribute("asynchronous").as_ulong() != 0)
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cerr << top->get_line() << ": warning: "
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<< "Process is marked asynchronous,"
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<< " but isn't really." << endl;
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return;
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}
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if (! top->synth_async(des))
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if (! top->synth_async(des)) {
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cerr << top->get_line() << ": internal error: "
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<< "is_asynchronous does not match "
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<< "sync_async results." << endl;
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return;
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}
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cerr << top->get_line() << ": info: thread is asynchronous." << endl;
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des->delete_process(top);
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}
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@ -100,6 +177,11 @@ void synth2(Design*des)
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/*
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* $Log: synth2.cc,v $
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* Revision 1.2 2002/07/01 00:54:21 steve
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* synth_asych of if/else requires redirecting the target
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* if sub-statements. Use NetNet objects to manage the
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* situation.
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*
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* Revision 1.1 2002/06/30 02:21:32 steve
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* Add structure for asynchronous logic synthesis.
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*
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